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參數(shù)資料
| 型號(hào)： | MC68HC05V7CFU |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | QFP-64 |
| 文件頁(yè)數(shù)： | 32/170頁(yè) |
| 文件大小： | 980K |
| 代理商： | MC68HC05V7CFU |
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SECTION 15: MESSAGE DATA LINK CONTROLLER
MOTOROLA
Page 113
MC68HC05V7 Specification Rev. 1.0
15.5.1.1
Operation
The clock for the digital filter is provided by the MUX Interface clock. At each positive edge
of the clock signal, the current state of the Receiver Physical Interface (RxP) signal is
sampled. The RxP signal state is used to determine whether the counter should increment
or decrement at the next negative edge of the clock signal.
The counter will increment if the input data sample is high but decrement if the input sample
is low. The counter will thus progress up towards ’15’ if, on average, the RxP signal remains
high or progress down towards ’0’ if, on average, the RxP signal remains low.
When the counter eventually reaches the value ’15’, the digital filter decides that the
condition of the RxP signal is at a stable logic level one and the Data Latch is set, causing
the Filtered Rx Data signal to become a logic level one. Furthermore, the counter is
prevented from overflowing and can only be decremented from this state.
Alternatively, should the counter eventually reach the value ’0’, the digital filter decides that
the condition of the RxP signal is at a stable logic level zero and the Data Latch is reset,
causing the Filtered Rx Data signal to become a logic level zero. Furthermore, the counter
is prevented from underflowing and can only be incremented from this state.
The Data Latch will retain its value until the counter next reaches the opposite end point,
signifying a definite transition of the RxP signal.
15.5.1.2
Performance
The performance of the digital filter is best described in the time domain rather than the
frequency domain.
If the level of the RxP signal transitions, then there will be a delay before that transition
appears at the Filtered Rx Data output signal. This delay will be between 15 and 16 clock
periods, depending on where the transition occurs with respect to the sampling points. This
’filter delay’ must be taken into account when performing message arbitration.
For example, if the frequency of the MUX Interface clock (f
MDLC
) is 1.0486MHz, then the
period (t
MDLC
) is 954ns and the maximum filter delay in the absence of noise will be
15.259us.
The effect of random noise on the RxP signal depends on the characteristics of the noise
itself. Narrow noise pulses on the RxP signal will be completely ignored if they are shorter
than the filter delay. This provides a degree of low pass filtering.
If noise occurs during a symbol transition, the detection of that transition may be delayed
by an amount equal to the length of the noise burst. This is just a reflection of the
uncertainty of where the transition is truly occurring within the noise.
Noise pulses that are wider than the filter delay, but narrower than the shortest allowable
symbol length will be detected by the next stage of the MDLC’s receiver as an invalid
symbol.
Noise pulses that are longer than the shortest allowable symbol length will normally be
detected as an invalid symbol or as invalid data when the frame’s CRC is checked.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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