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參數(shù)資料
| 型號(hào)： | MC68HC05X4 |
| 廠商： | Motorola, Inc. |
| 英文描述： | HCMOS Microcontroller Unit |
| 中文描述： | HCMOS微控制器 |
| 文件頁(yè)數(shù)： | 49/156頁(yè) |
| 文件大?。?/td> | 926K |
| 代理商： | MC68HC05X4 |
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Resets, Interrupts and Low Power Modes
Interrupts
MC68HC05X4 Rev 1.0
MOTOROLA
Resets, Interrupts and Low Power Modes
For More Information On This Product,
Go to: www.freescale.com
49
RESET pin
When the oscillator is running in a stable state, the MCU is reset when a
logic zero is applied to the RESET input for a minimum period of 1.5
machine cycles (t
CYC
). This pin contains an internal Schmitt Trigger as
part of its input to improve noise immunity.
Illegal address
reset
When an opcode fetch occurs from an address which is not part of the
RAM ($0050 – $00FF) or of the NVM ($0F00 – $1F00 and $1FF0 –
$1FFF) then the device is automatically reset.
Computer
operating properly
(COP) reset
The MCU contains a watchdog timer that automatically times out if not
reset (cleared) within a specific time by a program reset sequence. If the
COP watchdog timer is allowed to time-out, an internal reset is
generated to reset the MCU. Because the internal reset signal is used,
the MCU comes out of a COP reset in the same operating mode it was
in when the COP time-out was generated.
The COP reset function is enabled or disabled by a mask option.
Refer to
Computer operating properly (COP) watchdog timer
for
more information on the COP watchdog timer.
Interrupts
The MCU can be interrupted by five different sources, four maskable
hardware interrupts and one non-maskable software interrupt:
MCAN
Wired-OR function on ports A and B
Core timer
16-bit programmable timer
Software Interrupt instruction (SWI)
Interrupts cause the processor to save the register contents on the stack
and to set the interrupt mask (I-bit) to prevent additional interrupts. The
3-resets
F
Freescale Semiconductor, Inc.
n
.
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