參數(shù)資料
型號： MC68HC05X4DW
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： HCMOS Microcontroller Unit
中文描述： 8-BIT, MROM, 2.2 MHz, MICROCONTROLLER, PDSO28
封裝： SOIC-28
文件頁數(shù)： 67/156頁
文件大?。?/td> 926K
代理商： MC68HC05X4DW
Parallel input/output ports
Port registers
MC68HC05X4 Rev 1.0
MOTOROLA
Parallel input/output ports
For More Information On This Product,
Go to: www.freescale.com
67
5-ports
BPDE — Port B pull-down enable
1 = Enables pull-down on port B.
0 = Disables pull-down on port B.
BWE — Port B WOI enable
1 = Enables wired-OR interrupt on port B.
0 = Disables wired-OR interrupt on port B.
AWPS — Port A WOI and pull-down select
Addresses $00 and $04 in the memory map are shared by two pairs of
registers. The state of the AWPS bit determines which pair of registers
are accessible at any time. When AWPS is clear the port A data register
is found at $00, and the port A data direction register at $04. When
AWPS is set, $00 becomes the port A WOI enable register, and $04 the
port A pull-down enable register. See
Input/output programming
.
1 = The port A WOI enable and pull-down enable registers are
accessible.
0 = The port A data and data direction registers are accessible.
Port A data
direction register
(PADDR)
Writing a ‘1’ to any bit configures the corresponding bit in the port A data
register as an output; conversely, writing any bit to ‘0’ configures the
corresponding port A bit as an input.
Reset clears this register.
NOTE:
If the AWPS bit in the PCR is set then this location becomes the
port A pull-down enable register. Writing a ‘1’ to any bit enables the
pull-down on the corresponding port A line.
Port B data
direction register
(PBDDR)
Writing a ‘1’ to any bit configures the corresponding bit in the port B data
register as an output. Conversely, writing any bit to ‘0’ configures the
corresponding port B bit as an input.
Reset clears this register.
F
Freescale Semiconductor, Inc.
n
.
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