NON-DISCLOSURE
AGREEMENT
REQUIRED
Advance Information
MC68HC08AS20 —Rev. 4.1
368
Freescale Semiconductor
21.5 5.0 Volt DC Electrical Characteristics
Characteristic
Symbol
Min
Typ
Max
Unit
Output High Voltage
(ILoad = –2.0 mA) All Ports, RESET
VOH
VDD –0.8
—
V
Output Low Voltage
(ILoad = 1.6 mA) All Ports, RESET
VOL
——
0.4
V
Input High Voltage
All Ports, IRQ
s, RESET, OSC1
VIH
0.7 x VDD
—VDD
V
Input Low Voltage
All Ports, IRQ
s, RESET, OSC1
VIL
VSS
—
0.3 x VDD
V
VDD + VDDA/VDDAREF Supply Current
Run (see Note 3)
Wait (see Note 4)
Stop (see Note 5)
25
°C
–40
°C to +105 °C
25
°C with LVI Enabled
–40
°C to +105 °C with LVI Enabled
IDD
—
30
15
5
50
400
500
mA
A
I/O Ports Hi-Z Leakage Current
IL
——
± 1
A
Input Current
IIN
——
± 1
A
Capacitance
Ports (As Input or Output)
COUT
CIN
—
12
8
pF
Low-Voltage Reset Inhibit
VLVII
3.8
4.0
4.2
V
Low-Voltage Reset Recover
VLVIR
4.0
4.2
4.4
V
Low-Voltage Reset Inhibit/Recover Hysteresis
HLVI
100
200
500
mV
POR ReArm Voltage (see Note 6)
VPOR
0—
200
mV
POR Reset Voltage (see Note 7)
VPORRST
0—
800
mV
POR Rise Time Ramp Rate (see Note 8)
RPOR
0.02
—
V/ms
High COP Disable Voltage (see Note 9)
VHI
VDD
VDD + 2
V
NOTES:
1. VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = –40 °C to +105 °C, unless otherwise noted.
2. Typical values reflect average measurements at midpoint of voltage range, 25
°C only.
3. Run (Operating) IDD measured using external square wave clock source (fOP = 8.4 MHz). All inputs 0.2 V from rail.
No dc loads. Less than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capaci-
tance linearly affects run IDD. Measured with all modules enabled.
4. Wait IDD measured using external square wave clock source (fOP = 8.4 MHz). All inputs 0.2 Vdc from rail. No dc
loads. Less than 100 pF on all outputs, CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance
linearly affects wait IDD. Measured with all modules enabled.
5. Stop IDD measured with OSC1 = VSS.
6. Maximum is highest voltage that POR is guaranteed.
7. Maximum is highest voltage that POR is possible.
8. If minimum VDD is not reached before the internal POR reset is released, RST must be driven low externally until
minimum VDD is reached.