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參數(shù)資料
| 型號(hào)： | MC68HC08AS20FNR2 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, MICROCONTROLLER, PQCC52 |
| 封裝： | PLASTIC, LCC-52 |
| 文件頁數(shù)： | 44/96頁 |
| 文件大?。?/td> | 3243K |
| 代理商： | MC68HC08AS20FNR2 |
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5
MC68HC05E0
MOTOROLA
5-3
MEMORY AND ADDRESSING
address lines:
A13
– PD5
A14
– PD6
A15
– PD7
control signals:
P02
– PD0
R/W
– PD1
LIR
– PD4
chip select signals:
CS2
– PD2
CS3
– PD3
The MC68HC05E0 directly provides gated chip-select and read/write signals. A complete system
comprising MPU, program EPROM and RAM (optional) can thus be built without any additional
circuitry. An example of this basic system is shown in Figure 5-2. The R/W signal and the
chip-select signal for additional RAM (and additional I/O) is optionally available using Port D pins.
CSROM is intended to select the program ROM/EPROM and is valid in the address range $3000
to $FFFF. CS2 and CS3 select address ranges $0020 to $1FFF and $2000 to $2FFF respectively.
Larger, more versatile systems with more external memory and/or peripherals can be designed
with the inclusion of additional chip select logic. An example of an expanded system using an
MC74HC138 is shown in Figure 5-3. The gating of the chip selects with P02 (using the CS1 pin
on the MC74HC138) means that the output enable pins of the EPROM(s) and RAM(s) can be
grounded. If the memory’s chip select is not qualied by the clock, then its output enable pin should
be driven by P02 in order to avoid bus contention during the low period of P02. This type of
expanded system would be useful, for example, in a development environment where several
EPROM and/or RAM chips are required. Care should be taken to ensure that the loading
specication of the buses is not exceeded.
Table 5-1 Vector Addresses for Interrupts and Reset
Register
Flag name
Interrupt source
CPU interrupt
Vector address
N/A
Reset
RESETS
$FFFE – $FFFF
CCR
I-bit
Software
SWI
$FFFC – $FFFD
Interrupt control
INTFX
External (INTX)
RTI control
RTIF
Real time interrupt
IRQB
$FFFA – $FFFB
Interrupt control
WAKF
Wakje-up
Interrupt control
INTFA
Timer A
INT2
$FFF8 – $FFF9
Interrupt control
INTFB
Timer B
INT1
$FFF6 – $FFF7
SI S
IRQ/ACK
SPI/I2C
INT0
$FFF4 – $FFF5
49
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