Clock Generator Module (CGM)
Data Sheet
MC68HC08AS32A — Rev. 1
102
Clock Generator Module (CGM)
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MOTOROLA
The following conditions apply when the PLL is in automatic bandwidth control
mode:
The ACQ bit (see
5.5.2 PLL Bandwidth Control Register
) is a read-only
indicator of the mode of the filter. (See
5.3.2.2 Acquisition and Tracking
Modes
.)
The ACQ bit is set when the VCO frequency is within a certain tolerance,
TRK
, and is cleared when the VCO frequency is out of a certain tolerance,
UNT
. (See
5.9 Acquisition/Lock Time Specifications
for more
information.)
The LOCK bit is a read-only indicator of the locked state of the PLL.
The LOCK bit is set when the VCO frequency is within a certain tolerance,
LOCK
, and is cleared when the VCO frequency is out of a certain tolerance,
UNL
. (See
5.9 Acquisition/Lock Time Specifications
for more
information.)
CPU interrupts can occur if enabled (PLLIE = 1) when the PLL’s lock
condition changes, toggling the LOCK bit. (See
5.5.1 PLL Control
Register
.)
The PLL also can operate in manual mode (AUTO = 0). Manual mode is used by
systems that do not require an indicator of the lock condition for proper operation.
Such systems typically operate well below f
BUSMAX
and require fast startup.
The following conditions apply when in manual mode:
ACQ is a writable control bit that controls the mode of the filter. Before
turning on the PLL in manual mode, the ACQ bit must be clear.
Before entering tracking mode (ACQ = 1), software must wait a given time,
t
ACQ
(see
5.9 Acquisition/Lock Time Specifications
), after turning on the
PLL by setting PLLON in the PLL control register (PCTL).
Software must wait a given time, t
AL
, after entering tracking mode before
selecting the PLL as the clock source to CGMOUT (BCS = 1).
The LOCK bit is disabled.
CPU interrupts from the CGM are disabled.
5.3.2.4 Programming the PLL
Use this procedure to program the PLL:
1.
Choose the desired bus frequency, f
BUSDES
.
Example: f
BUSDES
= 8 MHz
2.
Calculate the desired VCO frequency, f
VCLKDES
.
f
VCLKDES
= 4
×
f
BUSDES
Example: f
VCLKDES
= 4
×
8 MHz = 32 MHz
F
Freescale Semiconductor, Inc.
n
.