Memory
Electrically Erasable Programmable ROM (EEPROM)
MC68HC08AS32A — Rev. 1
Data Sheet
MOTOROLA
Memory
47
EELAT — EEPROM Latch Control
This read/write bit latches the address and data buses for programming the
EEPROM array. EELAT cannot be cleared if EEPGM is still set. Reset clears
this bit.
1 = Buses configured for EEPROM programming
0 = Buses configured for normal read operation
AUTO — Automatic Termination of Program/Erase Cycle
When AUTO is set, EEPGM is cleared automatically after the program/erase
cycle is terminated by the state machine.
See note D for
2.5.1.7 EEPROM Programming
and
2.5.1.8 EEPROM Erasing
.
1 = Automatic clear of EEPGM is enabled
0 = Automatic clear of EEPGM is disabled
EEPGM — EEPROM Program/Erase Enable
This read/write bit initiates the program/erase state machine which applies the
programming/erasing voltage to the EEPROM array if the EELAT bit is set and
a write to a valid EEPROM location has occurred. Once a program/erase
sequence has been initiated, writing a 0 to EEPGM has no effect. The state
machine sequence must complete before the program/erase voltage is
removed from the array. The state machine will clear the EEPGM bit when the
program/erase sequence is completed in AUTO mode. In standard mode, the
EEPGM bit must be cleared to complete the sequence. Reset clears the
EEPGM bit and resets the program/erase state machine.
1 = EEPROM program/erase state machine initiated and EEPROM
programming/erasing power switched on
0 = No effect
NOTE:
Writing logic 0s to both the EELAT and EEPGM bits with a single instruction will
clear only EEPGM. A subsequent write of logic 0 to EELAT must be performed to
clear the bit. Both bits must be cleared to perform subsequent program/erase
cycles.
Table 2-4. EEPROM Program/Erase Mode Select
EEBPx
EERAS1
EERAS0
Mode
0
0
0
Byte program
0
0
1
Byte erase
0
1
0
Block erase
0
1
1
Bulk erase
1
X
X
No erase/program
X = don’t care
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.