參數(shù)資料
型號(hào): MC68HC08GP32AMFB
廠商: FREESCALE SEMICONDUCTOR INC
元件分類(lèi): 微控制器/微處理器
英文描述: 8-BIT, MROM, 8.2 MHz, MICROCONTROLLER, PQFP44
封裝: 10 X 10 MM, 0.80 MM PITCH, PLASTIC, QFP-44
文件頁(yè)數(shù): 49/258頁(yè)
文件大小: 1855K
代理商: MC68HC08GP32AMFB
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Serial Communications Interface (SCI) Module
MC68HC08GP32A MC68HC08GP16A Data Sheet, Rev. 1.0
142
Freescale Semiconductor
14.4.2.5 Inversion of Transmitted Output
The transmit inversion bit (TXINV) in SCI control register 1 (SCC1) reverses the polarity of transmitted
data. All transmitted values, including idle, break, start, and stop bits, are inverted when TXINV is 1. See
14.4.2.6 Transmitter Interrupts
These conditions can generate CPU interrupt requests from the SCI transmitter:
SCI transmitter empty (SCTE) — The SCTE bit in SCS1 indicates that the SCDR has transferred
a character to the transmit shift register. SCTE can generate a transmitter CPU interrupt request.
Setting the SCI transmit interrupt enable bit, SCTIE, in SCC2 enables the SCTE bit to generate
transmitter CPU interrupt requests.
Transmission complete (TC) — The TC bit in SCS1 indicates that the transmit shift register and the
SCDR are empty and that no break or idle character has been generated. The transmission
complete interrupt enable bit, TCIE, in SCC2 enables the TC bit to generate transmitter CPU
interrupt requests.
14.4.3 Receiver
Figure 14-6 shows the structure of the SCI receiver.
14.4.3.1 Character Length
The receiver can accommodate either 8-bit or 9-bit data. The state of the M bit in SCI control register 1
(SCC1) determines character length. When receiving 9-bit data, bit R8 in SCI control register 2 (SCC2)
is the ninth bit (bit 8). When receiving 8-bit data, bit R8 is a copy of the eighth bit (bit 7).
14.4.3.2 Character Reception
During an SCI reception, the receive shift register shifts characters in from the PTE1/RxD pin. The SCI
data register (SCDR) is the read-only buffer between the internal data bus and the receive shift register.
After a complete character shifts into the receive shift register, the data portion of the character transfers
to the SCDR. The SCI receiver full bit, SCRF, in SCI status register 1 (SCS1) becomes set, indicating that
the received byte can be read. If the SCI receive interrupt enable bit, SCRIE, in SCC2 is also set, the
SCRF bit generates a receiver CPU interrupt request.
14.4.3.3 Data Sampling
The receiver samples the PTE1/RxD pin at the RT clock rate. The RT clock is an internal signal with a
frequency 16 times the baud rate. To adjust for baud rate mismatch, the RT clock is resynchronized at
the following times (see Figure 14-7):
After every start bit
After the receiver detects a data bit change from 1 to 0 (after the majority of data bit samples at
RT8, RT9, and RT10 returns a valid 1 and the majority of the next RT8, RT9, and RT10 samples
returns a valid 0)
To locate the start bit, data recovery logic does an asynchronous search for a 0 preceded by three 1s.
When the falling edge of a possible start bit occurs, the RT clock begins to count to 16.
相關(guān)PDF資料
PDF描述
MC68HC08GP16AMBE 8-BIT, MROM, 8.2 MHz, MICROCONTROLLER, PDIP42
MC68HC08GP32AMB 8-BIT, MROM, 8.2 MHz, MICROCONTROLLER, PDIP42
MC68HC08GP16ACFB 8-BIT, MROM, 8.2 MHz, MICROCONTROLLER, PQFP44
MC68HC08GP16ACB 8-BIT, MROM, 8.2 MHz, MICROCONTROLLER, PDIP42
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