Timer Interface Module (TIM1)
MC68HC08GR32A MC68HC08GR16A Data Sheet, Rev. 0
210
Freescale Semiconductor
17.4.1 TIM1 Counter Prescaler
The TIM1 clock source is one of the seven prescaler outputs. The prescaler generates seven clock rates
from the internal bus clock. The prescaler select bits, PS[2:0], in the TIM1 status and control register
(T1SC) select the TIM1 clock source.
17.4.2 Input Capture
With the input capture function, the TIM1 can capture the time at which an external event occurs. When
an active edge occurs on the pin of an input capture channel, the TIM1 latches the contents of the TIM1
counter into the TIM1 channel registers, T1CHxH:T1CHxL. The polarity of the active edge is
programmable. Input captures can generate TIM1 central processor unit (CPU) interrupt requests.
17.4.3 Output Compare
With the output compare function, the TIM1 can generate a periodic pulse with a programmable polarity,
duration, and frequency. When the counter reaches the value in the registers of an output compare
channel, the TIM1 can set, clear, or toggle the channel pin. Output compares can generate TIM1 CPU
interrupt requests.
$0024
TIM1 Counter Modulo Register
Low (T1MODL)
Read:
Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1
Bit 0
Write:
Reset:
1111111
1
$0025
TIM1 Channel 0 Status and
Control Register (T1SC0)
Read:
CH0F
CH0IE
MS0B
MS0A
ELS0B
ELS0A
TOV0
CH0MAX
Write:
0
Reset:
0000000
0
$0026
TIM1 Channel 0 Register High
(T1CH0H)
Read:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Write:
Reset:
Indeterminate after reset
$0027
TIM1 Channel 0 Register Low
(T1CH0L)
Read:
Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1
Bit 0
Write:
Reset:
Indeterminate after reset
$0028
TIM1 Channel 1 Status and
Control Register (T1SC1)
Read:
CH1F
CH1IE
0
MS1A
ELS1B
ELS1A
TOV1
CH1MAX
Write:
0
Reset:
0000000
0
$0029
TIM1 Channel 1 Register High
(T1CH1H)
Read:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Write:
Reset:
Indeterminate after reset
$002A
TIM1 Channel 1 Register Low
(T1CH1L)
Read:
Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1
Bit 0
Write:
Reset:
Indeterminate after reset
Addr.
Register Name
Bit 7
654321
Bit 0
= Unimplemented
Figure 17-3. TIM1 I/O Register Summary (Continued)