General Description
MC68HC08GZ32 Data Sheet, Rev. 3
22
Freescale Semiconductor
Figure 1-2. MCU Block Diagram
SINGLE BREAKPOINT BREAK
MODULE
SYSTEM INTEGRATION
MODULE
PROGRAMMABLE TIMEBASE
MODULE
6-CHANNEL TIMER INTERFACE
MODULE
DUAL VOLTAGE
LOW-VOLTAGE INHIBIT MODULE
8-BIT KEYBOARD
ARITHMETIC/LOGIC
UNIT (ALU)
CPU
REGISTERS
M68HC08 CPU
CONTROL AND STATUS REGISTERS — 64 BYTES
USER ROM — 32,256 BYTES
USER RAM — 1536 BYTES
MONITOR ROM — 304 BYTES
USER ROM VECTOR SPACE — 52 BYTES
SINGLE EXTERNAL
INTERRUPT MODULE
PORT
A
DDRA
DD
R
C
PORTC
DDRD
POR
T
D
DDRE
PORTE
INTERNAL BUS
OSC1
OSC2
RST(3)
IRQ(3)
INTERRUPT MODULE
COMPUTER OPERATING
PROPERLY MODULE
PTA7/KBD7/
10-BIT ANALOG-TO-DIGITAL
CONVERTER MODULE
PTC6(1)
PTC5(1)
PTC4(1, 2)
PTC3(1, 2)
PTC2(1, 2)
PTC1/CANRX
(1, 2)
PTC0/CANTX
(1, 2)
PTD7/T2CH1(1)
PTD6/T2CH0(1)
PTD5/T1CH1(1)
PTD4/T1CH0(1)
PTD3/SPSCK(1)
PTD2/MOSI(1)
PTD1/MISO(1)
PTD0/SS/MCLK(1)
PTE1/RxD
PTE0/TxD
2-CHANNEL TIMER INTERFACE
MODULE
ENHANCED SERIAL
INTERFACE MODULE
SECURITY
MODULE
POWER-ON RESET
MODULE
MEMORY MAP
MODULE
MASK OPTION REGISTER 1–2
MODULE
MSCAN08
MODULE
POWER
VSS
VDD
VSSA
VDDA
1. Ports are software configurable with pullup device if input port, pullup or pulldown device for keyboard
2. Higher current drive port pins
3. Pin contains integrated pullup device
VDDAD/VREFH
VSSAD/VREFL
PTE5–PTE2
COMMUNICATIONS
CLOCK GENERATOR MODULE
CGMXFC
PHASE LOCKED LOOP
1–8 MHz OSCILLATOR
PORTB
D
DRB
PTB7/AD7–
PORTF
DDRF
PTF7/T2CH5
PORT
G
DDRG
PTG7/AD23–
PTF6/T2CH4
PTF5/T2CH3
PTF4/T2CH2
PTF3-PFT0(2)
SERIAL PERIPHERAL
INTERFACE MODULE
AD15–PTA0/
KBD0/AD8(1)
PTB0/AD0
PTG0/AD16