- 您現在的位置：買賣IC網 > PDF目錄45226 > MC68HC11A1MFU2 (ABILIS SYSTEMS) 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PQFP64 PDF資料下載
參數資料
| 型號： | MC68HC11A1MFU2 |
| 廠商： | ABILIS SYSTEMS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | QFP-64 |
| 文件頁數： | 109/158頁 |
| 文件大?。?/td> | 3803K |
| 代理商： | MC68HC11A1MFU2 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁當前第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁
SERIAL COMMUNICATIONS INTERFACE
MC68HC11A8
5-10
TECHNICAL DATA
5
5.8.4 Serial Communications Status Register (SCSR)
The serial communications status register (SCSR) provides inputs to the interrupt logic
circuits for generation of the SCI system interrupt.
TDRE — Transmit Data Register Empty
The transmit data register empty bit is set to indicate that the content of the serial com-
munications data register have been transferred to the transmit serial shift register.
This bit is cleared by reading the SCSR (with TDRE = 1) followed by a write to the
SCDR.
TC — Transmit Complete
The transmit complete bit is set at the end of a data frame, preamble, or break condi-
tion if:
1. TE = 1, TDRE = 1, and no pending data, preamble, or break is to be transmitted;
or
2. TE = 0, and the data, preamble, or break in the transmit shift register has been
transmitted.
The TC bit is a status flag which indicates that one of the above conditions have oc-
curred.
The TC bit is cleared by reading the SCSR (with TC set) followed by a write to the
SCDR.
RDRF — Receive Data Register Full
The receive data register full bit is set when the receiver serial shift register is transferred to
the SCDR. The RDRF bit is cleared when the SCSR is read (with RDRF set) followed by a
read of the SCDR.
IDLE — Idle Line Detect
The idle line detect bit, when set, indicates the receiver has detected an idle line. The IDLE
bitisclearedbyreadingtheSCSRwithIDLEsetfollowedbyreadingSCDR.OncetheIDLE
status flag is cleared, it will not be set again until after the RxD line has been active and be-
comes idle again.
OR — Overrun Error
Theoverrunerrorbitissetwhenthenextbyteisreadytobetransferredfromthereceiveshift
register to the SCDR which is already full (RDRF bit is set). When an overrun error occurs,
thedatawhichcausedtheoverrunislostandthedatawhichwasalreadyinSCDRisnotdis-
turbed. The OR is cleared when the SCSR is read (with OR set), followed by a read of the
SCDR.
7
654321
0
$102E
TDRE
TC
RDRF
IDLE
OR
NF
FE
0
SCSR
RESET
11000000
F
re
e
sc
a
le
S
e
m
ic
o
n
d
u
c
to
r,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
c
..
.
相關PDF資料 |
PDF描述 |
|---|---|
| MC68HC11A8BMP2 | 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PDIP48 |
| MC68HCP11A1VP2 | 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PDIP48 |
| MC68HC11A8P1 | 8-BIT, MROM, MICROCONTROLLER, PDIP48 |
| MC68HC11A1MP | 8-BIT, EEPROM, 2 MHz, MICROCONTROLLER, PDIP48 |
| MC68HC11A8VFN1 | 8-BIT, MROM, 3 MHz, MICROCONTROLLER, PQCC52 |
相關代理商/技術參數 |
參數描述 |
|---|---|
| MC68HC11A1MP | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:8-Bit Microcontrollers |
| MC68HC11A1MP2 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:HCMOS Single-Chip Microcontroller |
| MC68HC11A1P | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:8-Bit Microcontrollers |
| MC68HC11A1VFN | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:8-Bit Microcontrollers |
| MC68HC11A1VFN2 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:HCMOS Single-Chip Microcontroller |
發(fā)布緊急采購，3分鐘左右您將得到回復。