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參數(shù)資料
| 型號(hào)： | MC68HC11A8BCFU2 |
| 廠商： | MOTOROLA INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | HCMOS Single-Chip Microcontroller |
| 中文描述： | 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | QFP-64 |
| 文件頁(yè)數(shù)： | 91/158頁(yè) |
| 文件大?。?/td> | 776K |
| 代理商： | MC68HC11A8BCFU2 |
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MC68HC11A8
TECHNICAL DATA
RESETS, INTERRUPTS, AND LOW POWER MODES
MOTOROLA
9-11
9
When set, upon reset in bootstrap mode only, the small bootstrap loader program is
enabled. When clear, by reset in the other three modes, this ROM is disabled and ac-
cesses to this area are treated as external accesses.
SMOD — Special Mode
The special mode bit reflects the inverse of the MODB input pin at the rising edge of
reset. It is set if the MODB pin is low during reset. If MODB is high during reset, it is
cleared. This bit may be cleared under software control from the special modes, thus,
changing the operating mode of the MCU, but may never be set by software.
MDA — Mode Select A
The mode select A bit reflects the status of the MODA input pin at the rising edge of
reset. While the SMOD bit is set (special bootstrap or special test mode in effect) the
MDA bit may be written, thus, changing the operating mode, of the MCU. When the
SMOD bit is clear, the MDA bit is a read-only bit and the operating mode cannot be
changed without going through a reset sequence.
Table 9-5
summarizes the relationship between the SMOD and MDA bits and the
MODB and MODA input pins at the rising edge of reset.
IRV — Internal Read Visibility
The internal read visibility bit is used in the special modes (SMOD = 1) to affect visibil-
ity of internal reads on the expansion data bus. IRV is writeable only if SMOD = 1 and
returns to zero if SMOD = 0. If IRV is clear, visibility of internal reads is blocked. If the
bit is set, internal reads are visible on the external bus.
PSEL3, PSEL2, PSEL1, and PSEL0 — Priority Select
These four priority select bits are used to specify one I bit related interrupt source
which becomes the highest priority I bit related source (
Table 9-6
). These bits may be
written only while the I bit in CCR = 1 (interrupts masked).
Table 9-5 Mode Bits Relationship
Inputs
Mode Description
Latched at Reset
SMOD
0
0
1
1
MODB
1
1
0
0
1 = Logic High
MODA
0
1
0
1
MDA
0
1
0
1
Single Chip
Expanded Multiplexed
Special Bootstrap
Special Test
0 = Logic Low
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相關(guān)代理商/技術(shù)參數(shù) |
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| MC68HC11A8BCP2 | 制造商:MOTOROLA 制造商全稱(chēng):Motorola, Inc 功能描述:HCMOS Single-Chip Microcontroller |
| MC68HC11A8BMP2 | 制造商:MOTOROLA 制造商全稱(chēng):Motorola, Inc 功能描述:HCMOS Single-Chip Microcontroller |
| MC68HC11A8BVP2 | 制造商:MOTOROLA 制造商全稱(chēng):Motorola, Inc 功能描述:HCMOS Single-Chip Microcontroller |
| MC68HC11A8FN | 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:8-Bit Microcontrollers |
| MC68HC11A8FN1 | 制造商:Motorola Inc 功能描述: |
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