參數(shù)資料
型號： MC68HC11D0CFBE2
廠商： Freescale Semiconductor
文件頁數(shù)： 68/124頁
文件大?。?/td> 0K
描述： MCU 8-BIT 192 RAM 2MHZ 44-QFP
標準包裝： 480
系列： HC11
核心處理器： HC11
芯體尺寸： 8-位
速度： 2MHz
連通性： SCI，SPI
外圍設(shè)備： POR，WDT
輸入/輸出數(shù)： 26
程序存儲器類型： ROMless
RAM 容量： 192 x 8
電壓 - 電源 (Vcc/Vdd)： 4.5 V ~ 5.5 V
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 44-QFP
包裝： 托盤
RESETS AND INTERRUPTS
5-4
TECHNICAL DATA
5.1.6 CONFIG Register
Bits [7:4] and 0 — Not implemented
Always read zero
NOCOP — COP System Disable
This bit is cleared out of reset in normal modes, enabling the COP system. It is set out
of reset in special modes. NOCOP is writable once in normal modes and at any time
in special modes.
0 = The COP system is enabled as the MCU comes out of reset.
1 = The COP system is disabled and does not generate system resets.
ROMON — Enable On-Chip ROM
5.2 Effects of Reset
When a reset condition is recognized, the internal registers and control bits are forced
to an initial state. Depending on the cause of the reset and the operating mode, the
reset vector can be fetched from any of six possible locations. Refer to Table 5-2.
These initial states then control on-chip peripheral systems to force them to known
startup states, as follows:
5.2.1 CPU
After reset, the CPU fetches the restart vector from the appropriate address during the
first three cycles, and begins executing instructions. The stack pointer and other CPU
registers are indeterminate immediately after reset; however, the X and I interrupt
mask bits in the condition code register (CCR) are set to mask any interrupt requests.
Also, the S bit in the CCR is set to inhibit the STOP mode.
5.2.2 Memory Map
After reset, the INIT register is initialized to $00, putting the 192 bytes of RAM at loca-
tions $0040 through $00FF, and the control registers at locations $0000 through
$003F.
CONFIG — Configuration Control Register
$003F
Bit 7
654321
Bit 0
00000
NOCOP
ROMON
0
RESET:
00000
—
0
Table 5-2 Reset Cause, Reset Vector, and Operating Mode
Cause of Reset
Normal Mode Vector
Special Test or Bootstrap
POR or RESET Pin
$FFFE, FFFF
$BFFE, BFFF
Clock Monitor Failure
$FFFC, FFFD
$BFFC, $BFFD
COP Watchdog Time-out
$FFFA, FFFB
$BFFA, BFFB
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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