參數(shù)資料
型號: MC68HC11D0CFN2
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, 2 MHz, MICROCONTROLLER, PQCC44
封裝: PLASTIC, LCC-44
文件頁數(shù): 41/138頁
文件大小: 1047K
代理商: MC68HC11D0CFN2
MC68L11D0 Electrical Characteristics
MC68HC711D3 Data Sheet, Rev. 2.1
Freescale Semiconductor
135
B.2.6 Serial Peripheral Interface Timing
Num
Characteristic(1)
1. VDD = 3.0 Vdc to 5.5 Vdc, VSS = 0 Vdc, TA = TL to TH. All timing is shown with respect to 20% VDD and 70% VDD, unless
otherwise noted.
Symbol
1.0 MHz
2.0 MHz
Unit
Min
Max
Min
Max
Operating frequency
Master
Slave
fop(m)
fop(s)
dc
0.5
1.0
dc
0.5
2.0
fop
MHz
1
Cycle time
Master
Slave
tcyc(m)
tCYC(s)
2.0
1000
2.0
500
tcyc
ns
2
Enable lead time
Master(2)
Slave
2. Signal production depends on software.
tlead(m)
tlead(s)
500
250
ns
3
Enable lag time
Master(2)
Slave
tlag(m)
tlag(s)
500
250
ns
4
Clock (SCK) high time
Master
Slave
tw(SCKH)m
tw(SCKH)s
680
380
340
190
ns
5
Clock (SCK) low time
Master
Slave
tw(SCKL)m
tw(SCKL)s
680
380
340
190
ns
6
Data setup time (inputs)
Master
Slave
tsu(m)
tsu(s)
100
100
ns
7
Data hold time (inputs)
Master
Slave
th(m)
th(s)
100
100
ns
8
Access time (time to data active from high-impedance state)
Slave
ta
0
120
0
120
ns
9
Disable time (hold time to high-impedance state)
Slave
tdis
240
240
ns
10
Data valid (after enable edge)(3)
3. Assumes 100 pF load on all SPI pins.
tv(s)
240
240
ns
11
Data hold time (outputs) (after enable edge)
tho
0—0—
ns
12
Rise time (20% VDD to 70% VDD, CL = 200 pF)
SPI outputs (SCK, MOSI, and MISO)
SPI inputs (SCK, MOSI, MISO, and SS)
trm
trs
100
2.0
100
2.0
ns
s
13
Fall time (70% VDD to 20% VDD, CL = 200 pF)
SPI outputs (SCK, MOSI, and MISO)
SPI inputs (SCK, MOSI, MISO, and SS)
tfm
tfs
100
2.0
100
2.0
ns
s
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