參數(shù)資料
型號(hào): MC68HC11D0CFN2R2
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PQCC44
封裝: PLASTIC, LCC-44
文件頁(yè)數(shù): 113/131頁(yè)
文件大小: 1640K
代理商: MC68HC11D0CFN2R2
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)當(dāng)前第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)
MOTOROLA
SERIAL PERIPHERAL INTERFACE
MC68HC11D3
8-4
TECHNICAL DATA
8.3.1 Master In Slave Out
MISO is one of two unidirectional serial data signals. It is an input to a master device
and an output from a slave device. The MISO line of a slave device is placed in the
high impedance state if the slave device is not selected.
8.3.2 Master Out Slave In
The MOSI line is the second of the two unidirectional serial data signals. It is an output
from a master device and an input to a slave device. The master device places data
on the MOSI line a half-cycle before the clock edge that the slave device uses to latch
the data.
8.3.3 Serial Clock
SCK, an input to a slave device, is generated by the master device and synchronizes
data movement in and out of the device through the MOSI and MISO lines. Master and
slave devices are capable of exchanging a byte of information during a sequence of
eight clock cycles.
There are four possible timing relationships that can be chosen by using control bits
CPOL and CPHA in the serial peripheral control register (SPCR). Both master and
slave devices must operate with the same timing. The SPI clock rate select bits,
SPR[1:0], in the SPCR of the master device, select the clock rate. In a slave device,
SPR[1:0] have no effect on the operation of the SPI.
8.3.4 Slave Select
The SS input of a slave device must be externally asserted before a master device can
exchange data with the slave device. must be low before data transactions and must
stay low for the duration of the transaction.
The SS line of the master must be held high. If it goes low, a mode fault error flag
(MODF) is set in the serial peripheral status register (SPSR). To disable the mode fault
circuit, write a one in bit 5 of the port D data direction register. This sets the SS pin to
act as a general-purpose output. The other three lines are dedicated to the SPI when-
ever the serial peripheral interface is on.
The state of the master and slave CPHA bits affects the operation of SS. CPHA set-
tings should be identical for master and slave. When CPHA = 0, the shift clock is the
OR of SS with SCK. In this clock phase mode, SS must go high between successive
characters in an SPI message. When CPHA = 1, SS can be left low between succes-
sive SPI characters. In cases where there is only one SPI slave MCU, its SS line can
be tied to VSS as long as only CPHA = 1 clock mode is used.
8.4 SPI System Errors
Two system errors can be detected by the SPI system. The first type of error arises in
a multiple-master system when more than one SPI device simultaneously tries to be
a master. This error is called a mode fault. The second type of error, write collision,
相關(guān)PDF資料
PDF描述
MC68HC11D3CP1 8-BIT, MROM, 3 MHz, MICROCONTROLLER, PDIP40
MC68L11D0CFBE2R 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PQFP44
MC68HC711D3CFB 8-BIT, 2 MHz, MICROCONTROLLER, PQFP44
MC68HC11D3CFB 8-BIT, 2 MHz, MICROCONTROLLER, PQFP44
MC68L11D0CFBE2 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PQFP44
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MC68HC11D0CFN3 制造商: 功能描述: 制造商:undefined 功能描述:
MC68HC11D0CFNE2 功能描述:8位微控制器 -MCU 8B MCU 192 BYTES RAM RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
MC68HC11D0CFNE2R 功能描述:8位微控制器 -MCU 8B MCU 192 BYTES RAM RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
MC68HC11D0CFNE3 功能描述:8位微控制器 -MCU 8B MCU 192 BYTES RAM RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
MC68HC11D0CFNE3R 功能描述:8位微控制器 -MCU 8B MCU 192 BYTES RAM RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT