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參數(shù)資料
| 型號(hào)： | MC68HC11D0CFN3R2 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 3 MHz, MICROCONTROLLER, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁(yè)數(shù)： | 78/131頁(yè) |
| 文件大?。?/td> | 1640K |
| 代理商： | MC68HC11D0CFN3R2 |
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MOTOROLA
RESETS AND INTERRUPTS
MC68HC11D3
5-6
TECHNICAL DATA
5.2.7 COP
The COP watchdog system is enabled if the NOCOP control bit in the CONFIG regis-
ter is clear, and disabled if NOCOP is set. The COP rate is set for the shortest duration
time-out.
5.2.8 SCI
The reset condition of the SCI system is independent of the operating mode. At reset,
the SCI baud rate is indeterminate and must be established by a software write to the
BAUD register. All transmit and receive interrupts are masked and both the transmitter
and receiver are disabled so the port pins default to being general-purpose I/O lines.
The SCI frame format is initialized to an 8-bit character size. The send break and re-
ceiver wake-up functions are disabled. The TDRE and TC status bits in the SCI status
register are both set, indicating that there is no transmit data in either the transmit data
register or the transmit serial shift register. The RDRF, IDLE, OR, NF, and FE receive-
related status bits are cleared.
5.2.9 SPI
The SPI system is disabled by reset. The port pins associated with this function default
to being general-purpose I/O lines.
5.2.10 System
The memory system is configured for normal read operation. PSEL[3:0] are initialized
with the value $0101, causing the external IRQ pin to have the highest I-bit interrupt
priority. The IRQ pin is configured for level sensitive operation (for wired-OR systems).
The RBOOT, SMOD, and MDA bits in the HPRIO register reflect the status of the
MODB and MODA inputs at the rising edge of reset. The DLY control bit in OPTION is
set to specify that an oscillator start-up delay is imposed upon recovery from STOP.
The clock monitor system is disabled by CME equals zero.
5.3 Reset and Interrupt Priority
Resets and interrupts have a hardware priority that determines which reset or interrupt
is serviced first when simultaneous requests occur. Any maskable interrupt can be giv-
en priority over other maskable interrupts.
The first six interrupt sources are not maskable. The priority arrangement for these
sources is as follows:
1.
POR or RESET pin
2.
Clock monitor reset
3.
COP watchdog reset
4. XIRQ interrupt
5. Illegal opcode interrupt
6. Software interrupt (SWI)
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PDF描述 |
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| MC68L11D0CFB2R2 | 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PQFP44 |
| MC68HC11D3CFB1 | 8-BIT, OTPROM, 1 MHz, MICROCONTROLLER, PQFP44 |
| MC68HC11D3CP1 | 8-BIT, MROM, 1 MHz, MICROCONTROLLER, PDIP40 |
| MC68HC11D3CP1 | 8-BIT, MROM, 1 MHz, MICROCONTROLLER, PDIP40 |
| MC68HC11D0CFN3 | 8-BIT, MROM, 3 MHz, MICROCONTROLLER, PQCC44 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC68HC11D0CFNE2 | 功能描述:8位微控制器 -MCU 8B MCU 192 BYTES RAM RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| MC68HC11D0CFNE2R | 功能描述:8位微控制器 -MCU 8B MCU 192 BYTES RAM RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| MC68HC11D0CFNE3 | 功能描述:8位微控制器 -MCU 8B MCU 192 BYTES RAM RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| MC68HC11D0CFNE3R | 功能描述:8位微控制器 -MCU 8B MCU 192 BYTES RAM RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| MC68HC11D0CP3 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller |
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