參數(shù)資料
型號(hào)： MC68HC11D0CP3
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 3 MHz, MICROCONTROLLER, PDIP40
封裝： PLASTIC, DIP-40
文件頁數(shù)： 44/124頁
文件大?。?/td> 6875K
代理商： MC68HC11D0CP3
CENTRAL PROCESSING UNIT
3-6
TECHNICAL DATA
terrupt occurred. The X interrupt mask bit is set only by hardware (or acknowledge). X
is cleared only by program instruction (TAP, where the associated bit of A is 0; or RTI,
where bit 6 of the value loaded into the CCR from the stack has been cleared). There
is no hardware action for clearing X.
3.1.6.8 Stop Disable (S)
Setting the STOP disable (S) bit prevents the STOP instruction from putting the
M68HC11 into a low-power stop condition. If the STOP instruction is encountered by
the CPU while the S bit is set, it is treated as a no-operation (NOP) instruction, and
processing continues to the next instruction. S is set by reset —STOP disabled by de-
fault.
3.2 Data Types
The M68HC11 CPU supports the following data types:
Bit data
8-bit and 16-bit signed and unsigned integers
16-bit unsigned fractions
16-bit addresses
A byte is eight bits wide and can be accessed at any byte location. A word is composed
of two consecutive bytes with the most significant byte at the lower value address. Be-
cause the M68HC11 is an 8-bit CPU, there are no special requirements for alignment
of instructions or operands.
3.3 Opcodes and Operands
The M68HC11 family of microcontrollers uses 8-bit opcodes. Each opcode identifies
a particular instruction and associated addressing mode to the CPU. Several opcodes
are required to provide each instruction with a range of addressing capabilities. Only
256 opcodes would be available if the range of values were restricted to the number
able to be expressed in 8-bit binary numbers.
A four-page opcode map has been implemented to expand the number of instructions.
An additional byte, called a prebyte, directs the processor from page 0 of the opcode
map to one of the other three pages. As its name implies, the additional byte precedes
the opcode.
A complete instruction consists of a prebyte, if any, an opcode, and zero, one, two, or
three operands. The operands contain information the CPU needs for executing the
instruction. Complete instructions can be from one to five bytes long.
3.4 Addressing Modes
Six addressing modes; immediate, direct, extended, indexed, inherent, and relative,
detailed in the following paragraphs, can be used to access memory. All modes except
inherent mode use an effective address. The effective address is the memory address
from which the argument is fetched or stored, or the address from which execution is
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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