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參數(shù)資料
| 型號(hào)： | MC68HC11D3CFB1 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 3 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | QFP-44 |
| 文件頁數(shù)： | 74/131頁 |
| 文件大?。?/td> | 1640K |
| 代理商： | MC68HC11D3CFB1 |
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MC68HC11D3
RESETS AND INTERRUPTS
MOTOROLA
TECHNICAL DATA
5-3
Semiconductor wafer processing causes variations of the RC time-out values between
individual devices. An E-clock frequency below 10 kHz is detected as a clock monitor
error. An E-clock frequency of 200 kHz or more prevents clock monitor errors. Using
the clock monitor function when the E clock is below 200 kHz is not recommended.
Special considerations are needed when a STOP instruction is executed and the clock
monitor is enabled. Because the STOP function causes the clocks to be halted, the
clock monitor function generates a reset sequence if it is enabled at the time the STOP
mode was initiated. Before executing a STOP instruction, clear the CME bit in the OP-
TION register to zero to disable the clock monitor. After recovery from STOP, set the
CME bit to logic one to enable the clock monitor.
5.1.5 Option Register
*Can be written only once in first 64 cycles out of reset in normal modes, or at any time in special modes.
Bits [7:6] and 2 — Not implemented
Always read zero
IRQE — Configure IRQ for Edge Sensitive Only Operation
This bit can be written only once during the first 64 E-clock cycles after reset in normal
modes.
0 = Low level recognition
1 = Falling edge recognition
DLY — Enable Oscillator Startup Delay
This bit is set during reset and can be written only once during the first 64 E-clock cy-
cles after reset in normal modes. If an external clock source rather than a crystal is
used, the stabilization delay can be inhibited because the clock source is assumed to
be stable.
0 = No stabilization delay on exit from STOP
1 = Stabilization delay enabled on exit from STOP
CME — Clock Monitor Enable
This control bit can be read or written at any time and controls whether or not the in-
ternal clock monitor circuit triggers a reset sequence when the system clock is slow or
absent. When it is clear, the clock monitor circuit is disabled. When it is set, the clock
CR[1:0] — COP Timer Rate Select
These control bits determine a scaling factor for the watchdog timer.
OPTION — System Configuration Options
$0039
Bit 7
654321
Bit 0
0
IRQE*
DLY*
CME
0
CR1*
CR0*
RESET:
00010000
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| MC68HC11D3CFB3 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:ROM-based high-performance microcontrollers |
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| MC68HC11D3CFN2 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Microcontrollers |
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