參數(shù)資料
型號： MC68HC11D3CP1
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 1 MHz, MICROCONTROLLER, PDIP40
封裝： PLASTIC, DIP-40
文件頁數(shù)： 75/124頁
文件大小： 6875K
代理商： MC68HC11D3CP1
RESETS AND INTERRUPTS
5-10
TECHNICAL DATA
5.4.2 Non-Maskable Interrupt Request XIRQ
Non-maskable interrupts are useful because they can always interrupt CPU opera-
tions. The most common use for such an interrupt is for serious system problems, such
as program runaway or power failure. The XIRQ input is an updated version of the
nonmaskable NMI input of earlier MCUs.
Upon reset, both the X bit and I bits of the CCR are set to inhibit all maskable interrupts
and XIRQ. After minimum system initialization, software can clear the X bit by a TAP
instruction, enabling XIRQ interrupts. Thereafter, software cannot set the X bit. Thus,
an XIRQ interrupt is a nonmaskable interrupt. Because the operation of the I-bit-relat-
ed interrupt structure has no effect on the X bit, the internal XIRQ pin remains non-
masked. In the interrupt priority logic, the XIRQ interrupt has a higher priority than any
source that is maskable by the I bit. All I-bit-related interrupts operate normally with
their own priority relationship.
When an I-bit-related interrupt occurs, the I bit is automatically set by hardware after
stacking the CCR byte. The X bit is not affected. When an X-bit-related interrupt oc-
curs, both the X and I bits are automatically set by hardware after stacking the CCR.
A return from interrupt instruction restores the X and I bits to their pre-interrupt request
state.
5.4.3 Illegal Opcode Trap
Because not all possible opcodes or opcode sequences are defined, the MCU in-
cludes an illegal opcode detection circuit, which generates an interrupt request. When
an illegal opcode is detected and the interrupt is recognized, the current value of the
program counter is stacked. After interrupt service is complete, reinitialize the stack
pointer so repeated execution of illegal opcodes does not cause stack underflow. Left
uninitialized, the illegal opcode vector can point to a memory location that contains an
illegal opcode. This condition causes an infinite loop that causes stack underflow. The
stack grows until the system crashes.
The illegal opcode trap mechanism works for all unimplemented opcodes on all four
opcode map pages. The address stacked as the return address for the illegal opcode
interrupt is the address of the first byte of the illegal opcode. Otherwise, it would be
almost impossible to determine whether the illegal opcode had been one or two bytes.
Table 5-5 Stacking Order on Entry to Interrupts
Memory Location
CPU Registers
SP
PCL
SP – 1
PCH
SP –2
IYL
SP – 3
IYH
SP – 4
IXL
SP – 5
IXH
SP – 6
ACCA
SP – 7
ACCB
SP – 8
CCR
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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