Timing System
Data Sheet
M68HC11E Family — Rev. 5
154
Timing System
MOTOROLA
9.4.7 Timer Interrupt Mask 1 Register
Use this 8-bit register to enable or inhibit the timer input capture and output
compare interrupts.
OC1I–OC4I — Output Compare x Interrupt Enable Bits
If the OCxI enable bit is set when the OCxF flag bit is set, a hardware interrupt
sequence is requested.
I4/O5I — Input Capture 4/Output Compare 5 Interrupt Enable Bit
When I4/O5 in PACTL is 1, I4/O5I is the input capture 4 interrupt enable bit.
When I4/O5 in PACTL is 0, I4/O5I is the output compare 5 interrupt enable bit.
IC1I–IC3I — Input Capture x Interrupt Enable Bits
If the ICxI enable bit is set when the ICxF flag bit is set, a hardware interrupt
sequence is requested.
NOTE:
Bits in TMSK1 correspond bit for bit with flag bits in TFLG1. Bits in TMSK1 enable
the corresponding interrupt sources.
9.4.8 Timer Interrupt Flag 1 Register
Bits in this register indicate when timer system events have occurred. Coupled with
the bits of TMSK1, the bits of TFLG1 allow the timer subsystem to operate in either
a polled or interrupt driven system. Each bit of TFLG1 corresponds to a bit in
TMSK1 in the same position.
Clear flags by writing a 1 to the corresponding bit position(s).
OC1F–OC4F — Output Compare x Flag
Set each time the counter matches output compare x value
I4/O5F — Input Capture 4/Output Compare 5 Flag
Set by IC4 or OC5, depending on the function enabled by I4/O5 bit in PACTL
IC1F–IC3F — Input Capture x Flag
Set each time a selected active edge is detected on the ICx input line
Address:
$1022
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
OC1I
OC2I
OC3I
OC4I
I4/O5I
IC1I
IC2I
IC3I
0
0
0
0
0
0
0
0
Figure 9-17. Timer Interrupt Mask 1 Register (TMSK1)
Address:
$1023
Bit 7
6
4
3
2
1
Bit 0
Read:
Write:
Reset:
OC1F
OC2F
OC3F
OC4F
I4/O5F
IC1F
IC2F
IC3F
0
0
0
0
0
0
0
0
Figure 9-18. Timer Interrupt Flag 1 Register (TFLG1)
F
Freescale Semiconductor, Inc.
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