參數(shù)資料
型號(hào)： MC68HC11KA4TS
廠商： Motorola, Inc.
英文描述： KPT 3C 3#16 PIN PLUG
中文描述： 8位微控制器
文件頁數(shù)： 33/68頁
文件大?。?/td> 365K
代理商： MC68HC11KA4TS
MC68HC11KA4
MC68HC11KA4TS/D
MOTOROLA
33
DDA[7:0] —Data Direction for Port A
0 = Bits set to zero to configure corresponding I/O pin for input only
1 = Bits set to one to configure corresponding I/O pin for output
Reset state is mode dependent. In single-chip or bootstrap modes, port B pins are high impedance in-
puts with selectable internal pull-up resistors. In expanded or test modes, port B pins are high order ad-
dress outputs and PORTB is not in the memory map.
DDB[7:0] — Data Direction for Port B
0 = Bits set to zero to configure corresponding I/O pin for input only
1 = Bits set to one to configure corresponding I/O pin for output
Reset state is mode dependent. In single-chip or bootstrap modes, port F pins are high-impedance in-
puts with selectable internal pull-up resistors. In expanded or test modes, port F pins are low order ad-
dress outputs and PORTF is not in the memory map.
DDRA
— Data Direction Register for Port A
$0001
Bit 7
6
5
4
3
2
1
Bit 0
DDA7
DDA6
DDA5
DDA4
DDA3
DDA2
DDA1
DDA0
RESET:
0
0
0
0
0
0
0
0
PORTB
—Port B Data
$0004
Bit 7
6
5
4
3
2
1
Bit 0
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
S. Chip or
Boot:
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
RESET:
U
U
U
U
U
U
U
U
Expan. or
Test:
ADDR15
ADDR14
ADDR13
ADDR12
ADDR11
ADDR10
ADDR9
ADDR8
DDRB
— Data Direction Register for Port B
$0002
Bit 7
6
5
4
3
2
1
Bit 0
DDB7
DDB6
DDB5
DDB4
DDB3
DDB2
DDB1
DDB0
RESET:
0
0
0
0
0
0
0
0
PORTF
— Port F Data
$0005
Bit 7
6
5
4
3
2
1
Bit 0
PF7
PF6
PF5
PF4
PF3
PF2
PF1
PF0
S. Chip or
Boot:
PF7
PF6
PF5
PF4
PF3
PF2
PF1
PF0
RESET:
U
U
U
U
U
U
U
U
Expan. or
Test:
ADDR7
ADDR6
ADDR5
ADDR4
ADDR3
ADDR2
ADDR1
ADDR0
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