Electrical Specifications
Data Sheet
M68HC12B Family — Rev. 9.0
344
Electrical Specifications
MOTOROLA
The general idea of this circuit implementation is to supply VFP from a dc-dc
converter. This dc-dc converter, like most, provides a shutdown feature which
allows the converter’s output to be shut off. When the SHDN pin on the converter
is pulled high, as the 10-k
pullup resistor (R1) does, the output V
Out is shorted to
the VDD supply. This requires that the programming and erasing routines assert a
port pin on the MCU to turn on the converter and supply the 12-volt programming
voltage during the programming or erasing cycle. Simple programming and erasing
routines, such as those shown earlier in this application note, will no longer suffice.
By implementing this solution, VFP is tied to VDD on power-up and power-down,
ensuring that they rise and fall together. Capacitors C5 and C6 are the normal
decoupling capacitors on the VDD supply lines. C3 is used to reduce
electromagnetic interference (EMI) in the circuit. If C3 is too large, VFP will not be
allowed to fall with VDD, potentially causing data corruption in the FLASH array.
(Refer to Figure 19-3.) C4 is where the dc-dc converter stores charge to supply
VOut to the target device. The supply must be able to source approximately 30 mA
of current for at least 20
s (based on programming cycle requirements) and 4 mA
of current for at least 10 ms (based on erase cycle requirements).
A certain degree of experimentation might be required when selecting C4 and C3.
When trying different capacitor values, always monitor the effects on VFP decay
during power-down and current supplied to the VFP pin.
R1 must be no larger than 10 k
, to make certain that the SHDN pin on the dc-dc
converter is never allowed to fall below VDD unless the output pin of the
microcontroller is driven low. The external pullup ensures this behavior, no matter
what port pin is used on the microcontroller or what the internal structure of that pin
looks like. Without a strong enough pullup resistor on R1, the voltage on the SHDN
pin might drop during a reset event, causing the dc-dc converter to activate and
begin driving the voltage on VOut to begin to rise to 12 volts. This would result in
data corruption in the FLASH.
NOTE:
Figure 19-2 is different from the recommended circuit shown in information about
ST662A from ST Microelectronics, but it is correct. The change is in the location of
the capacitor C4, which is now placed between VDD and VFP. This change was
implemented with the cooperation of ST Microelectronics to aid in tracking a rapidly
has been verified with the Maxim Integrated Products device (MAX662).
Be certain that VFP decays with VDD, as shown in Figure 19-4, as new capacitance values are tested. The rate of decay of the VDD supply powering down will help
define how large the C3 capacitance can be made.