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M68HC16 Z SERIES
STANDBY RAM MODULE
USER’S MANUAL
6-3
ISB (SRAM standby current) values may vary while VDD transitions occur. Refer to AP- sumption specifications.
6.6 Reset
Reset places the SRAM in low-power stop mode, enables program space access, and
clears the base address registers and the register lock bit. These actions make it pos-
sible to write a new base address into the ROMBAH and ROMBAL registers.
When a synchronous reset occurs while a byte or word SRAM access is in progress,
the access is completed. If reset occurs during the first word access of a long-word
operation, only the first word access is completed. If reset occurs during the second
word access of a long-word operation, the entire access is completed. Data being read
from or written to the RAM may be corrupted by an asynchronous reset. For more in-
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Freescale Semiconductor, Inc.
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