MOTOROLA
ELECTRICAL CHARACTERISTICS
M68HC16 Z SERIES
A-24
USER’S MANUAL
30
CLKOUT Low to Data In Invalid (Fast Cycle Hold)
7tCLDI
10
—
ns
30A
tCLDH
—72
ns
31
DSACK[1:0] Asserted to Data In Valid9
tDADI
—46
ns
33
Clock Low to BG Asserted/Negated
tCLBAN
—23
ns
35
BR Asserted to BG Asserted
10tBRAGA
1—
tcyc
37
BGACK Asserted to BG Negated
tGAGN
12
tcyc
39
BG Width Negated
tGH
2—
tcyc
39A
BG Width Asserted
tGA
1—
tcyc
46
R/W Width Asserted (Write or Read)
tRWA
115
—
ns
46A
R/W Width Asserted (Fast Write or Read Cycle)
tRWAS
70
—
ns
47A
Asynchronous Input Setup Time
BR, BGACK, DSACK[1:0], BERR, AVEC, HALT
tAIST
5—
ns
47B
Asynchronous Input Hold Time
tAIHT
12
—
ns
48
DSACK[1:0] Asserted to BERR, HALT Asserted
11tDABA
—30
ns
53
Data Out Hold from Clock High
tDOCH
0—
ns
54
Clock High to Data Out High Impedance
tCHDH
—23
ns
55
R/W Asserted to Data Bus Impedance Change
tRADC
32
—
ns
70
Clock Low to Data Bus Driven (Show Cycle)
tSCLDD
023
ns
71
Data Setup Time to Clock Low (Show Cycle)
tSCLDS
10
—
ns
72
Data Hold from Clock Low (Show Cycle)
tSCLDH
10
—
ns
73
BKPT Input Setup Time
tBKST
10
—
ns
74
BKPT Input Hold Time
tBKHT
10
—
ns
75
Mode Select Setup Time, DATA[15:0], MODCLK, BKPT pins
tMSS
20
—
tcyc
76
Mode Select Hold Time, DATA[15:0], MODCLK, BKPT pins
tMSH
0—
ns
77
tRSTA
4—
tcyc
78
tRSTR
—10
tcyc
100
CLKOUT High to Phase 1 Asserted
14tCHP1A
340
ns
101
CLKOUT High to Phase 2 Asserted
14tCHP2A
340
ns
102
Phase 1 Valid to AS or DS Asserted
14tP1VSA
10
—
ns
103
Phase 2 Valid to AS or DS Asserted
14tP2VSN
10
—
ns
104
AS or DS Valid to Phase 1 Negated
14tSAP1N
10
—
ns
105
AS or DS Negated to Phase 2 Negated
14tSNP2N
10
—
ns
NOTES:
Table A-17 20.97-MHz AC Timing (Continued)
(V
DD
and V
DDSYN
= 5.0 Vdc
± 5%, V
SS
= 0 Vdc, T
A
= T
L
to T
H)
1
Num
Characteristic
Symbol
Min
Max
Unit