TABLE OF CONTENTS (Continued)
Paragraph
Page
Number
Title
Number
MOTOROLA
MC68HC681 USER’S MANUAL
vii
4.3.5.1
Channel A Receiver Clock Select - CSRA[7:4]............. 4-16
4.3.5.2
Channel A Transmitter Clock Select - CSRA[3:0]......... 4-16
4.3.6
Channel B Clock-Select Register (CSRB)................................ 4-17
4.3.6.1
Channel B Receiver Clock Select - CSRB[7:4]............. 4-17
4.3.6.2
Channel B Transmitter Clock Select - CSRB[3:0]......... 4-17
4.3.7
Channel A Command Register (CRA)...................................... 4-17
4.3.7.1
CRA[7]. ......................................................................... 4-17
4.3.7.2
Channel A Miscellaneous Commands - CRA[6:4]. ....... 4-17
4.3.7.3
Channel A Transmitter Commands - CRA[3:2]............. 4-18
4.3.7.4
Channel A Receiver Commands - CRA[1:0]................. 4-18
4.3.8
Channel B Command Register (CRB)...................................... 4-19
4.3.9
Channel A Status Register (SRA) ............................................ 4-19
4.3.9.1
Channel A Received Break - SRA[7]. ........................... 4-19
4.3.9.2
Channel A Framing Error - SRA[6]. .............................. 4-19
4.3.9.3
Channel A Parity Error - SRA[5]. .................................. 4-19
4.3.9.4
Channel A Overrun Error - SRA[4]. .............................. 4-19
4.3.9.5
Channel A Transmitter Empty - SRA[3]. ....................... 4-19
4.3.9.6
Channel A Transmitter Ready - SRA[2]........................ 4-20
4.3.9.7
Channel A FIFO Full - SRA[1]. ..................................... 4-20
4.3.9.8
Channel A Receiver Ready - SRA[0]............................ 4-20
4.3.10
Channel B Status Register (SRB) ............................................ 4-20
4.3.11
Output Port Configuration Register (OPCR) ............................ 4-20
4.3.11.1
OP7 Output Select - OPCR[7]. ..................................... 4-20
4.3.11.2
OP6 Output Select - OPCR[6]. ..................................... 4-20
4.3.11.3
OP5 Output Select - OPCR[5]. ..................................... 4-20
4.3.11.4
OP4 Output Select - OPCR[4]. ..................................... 4-20
4.3.11.5
OP3 Output Select - OPCR[3:2]. .................................. 4-21
4.3.11.6
OP2 Output Select - OPCR[1:0]. .................................. 4-21
4.3.12
Output Port Register - OPR[7:0]............................................... 4-21
4.3.13
Auxiliary Control Register (ACR) .............................................. 4-21
4.3.13.1
Baud-Rate Generator Set Select - ACR[7]. .................. 4-21
4.3.13.2
Counter/Timer Mode and Clock Source
Select — ACR[6:4]. .......................................................4-22
4.3.13.3
IP3, IP2, IP1, and IP0 Change-of-State Interrupt
Enable — ACR[3:0]. .....................................................4-22
4.3.14
Input Port Change Register (IPCR).......................................... 4-22
4.3.14.1
IP3, IP2, IP1, and IP0 Change of State - IPCR[7:4]. .... 4-22
4.3.14.2
IP31 IP2F IP1, and IP0 Current State — IPCR[3:0]. .... 4-22
4.3.15
Interrupt Status Register (ISR) ................................................. 4-22
4.3.15.1
Input Port Change Status - ISR[7]. .............................. 4-23
4.3.15.2
Channel B Change in Break — ISR[6].......................... 4-23
4.3.15.3
Channel B Receiver Ready or FIFO Full — ISR[5]....... 4-23
F
re
e
sc
a
le
S
e
m
ic
o
n
d
u
c
to
r,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
c
..
.