
MOTOROLA
C-16
MC68HC05B6
Rev. 4
MC68HC705B5
14
Figure C-8
RAM parallel bootstrap schematic diagram
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB6
PB7
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
VDD
TCAP2
TCMP2
TCMP1
PLMB
PLMA
SCLK
TDO
RDI
VRH
VRL
PD7
PD6
PD5
PD3
PD2
PD1
PD0
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
NC
OSC1
OSC2
TCAP1
IRQ
RESET
PD4
VPP6
VSS
A0
A1
A2
A3
A4
A5
A6
A7
D0
D1
D2
D3
D4
D5
D6
D7
GND
14
OE
A8
A9
A10
A11
A12
CE
VCC
PGM
VPP
20
23
2
25
24
22
10
9
8
7
6
5
4
3
1
26
NC
27
28
21
12
13
15
16
17
18
19
11
+5V
3 x 4.7k
+5V
+5V
16 x 100k
1
2
P1
GND
+5V
100
μ
F
22pF
4.0 MHz
22pF
1N914
1k
1.0
μ
F
10M
100k
1N914
RESET
RUN
0.01
μ
F
U1
2764
+5V
18 x 100 k
+
+
MC68HC705B5
TPG