參數資料
型號： MC68HC705C8ACP
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： HCMOS Microcontroller Unit
中文描述： 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDIP40
封裝： PLASTIC, DIP-40
文件頁數： 54/108頁
文件大?。?/td> 718K
代理商： MC68HC705C8ACP
External Interrupt Module (IRQ)
MC68HC705KJ1 MC68HRC705KJ1 MC68HLC705KJ1 Data Sheet, Rev. 4.1
54
Freescale Semiconductor
If edge- and level-sensitive triggering is selected, a rising edge or a high level on a PA0–PA3 pin latches
an external interrupt request. Edge- and level-sensitive triggering allows the use of multiple wired-OR
external interrupt sources. As long as any source is holding a PA0–PA3 pin high, an external interrupt
request is latched, and the CPU continues to execute the interrupt service routine.
If edge-sensitive only triggering is selected, a rising edge on a PA0–PA3 pin latches an external interrupt
request. A subsequent external interrupt request can be latched only after the voltage level of the previous
interrupt signal returns to logic 0 and then rises again to logic 1.
NOTE
The BIH and BIL instructions apply only to the level on the IRQ/V
PP
pin itself
and not to the output of the logic OR function with the PA0
–
PA3 pins. The
state of the individual port A pins can be checked by reading the
appropriate port A pins as inputs.
Enabled PA0
–
PA3 pins cause an IRQ interrupt regardless of whether these
pins are configured as inputs or outputs.
The IRQ pin has an internal Schmitt trigger. The optional external interrupts
(PA0
–
PA3) do not have internal Schmitt triggers.
The interrupt mask bit (I) in the condition code register (CCR) disables all
maskable interrupt requests, including external interrupt requests.
5.4 IRQ Status and Control Register
The IRQ status and control register (ISCR) controls and monitors operation of the IRQ module. All unused
bits in the ISCR read as logic 0s. The IRQF bit is cleared and the IRQE bit is set by reset.
IRQR — Interrupt Request Reset Bit
This write-only bit clears the external interrupt request flag.
1 = Clears external interrupt and IRQF bit
0 = No effect on external interrupt and IRQF bit
IRQF — External Interrupt Request Flag
The external interrupt request flag is a clearable, read-only bit that is set when an external interrupt
request is pending. Reset clears the IRQF bit.
1 = External interrupt request pending
0 = No external interrupt request pending
IRQE — External Interrupt Request Enable Bit
This read/write bit enables external interrupts. Reset sets the IRQE bit.
1 = External interrupt requests enabled
0 = External interrupt requests disabled
Address:
$000A
Bit 7
6
5
4
3
2
1
Bit 0
Read:
IRQE
0
0
0
IRQF
0
0
0
Write:
R
IRQR
Reset:
1
0
0
0
0
0
0
0
= Unimplemented
R
= Reserved
Figure 5-4. IRQ Status and Control Register (ISCR)
相關PDF資料
PDF描述
MC68HC705C8ACFS HCMOS Microcontroller Unit
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MC68HC705C8ACFB HCMOS Microcontroller Unit
MC68HC705C8ACB HCMOS Microcontroller Unit
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相關代理商/技術參數
參數描述
MC68HC705C8ACPB 制造商:Freescale Semiconductor 功能描述:
MC68HC705C8ACPE 制造商:Freescale Semiconductor 功能描述:
MC68HC705C8AFNE 功能描述:8位微控制器 -MCU HC05 CORE + 8K RAM + EPR RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數據總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數據 RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT
MC68HC705C8AFU 制造商:Rochester Electronics LLC 功能描述:8-BIT MCU W/BLANK EPROM - Bulk
MC68HC705C8AVFB 制造商:Rochester Electronics LLC 功能描述:- Bulk
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