參數(shù)資料
型號: MC68HC705E6MDWR2
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDSO28
封裝: PLASTIC, SOIC-28
文件頁數(shù): 83/140頁
文件大小: 1141K
代理商: MC68HC705E6MDWR2
Core Timer
Real time interrupts (RTI)
MC68HC05E6 — Rev. 1.0
MOTOROLA
Core Timer
47
periods can be attained using the CTIMER overflow function to
increment a temporary RAM storage location thereby simulating a 16-bit
(or more) counter.
The power-on cycle clears the entire counter chain and begins clocking
the counter. After tPORL cycles, the power-on reset circuit is released,
which again clears the counter chain and allows the device to come out
of reset. At this point, if RESET is not asserted, the timer will start
counting up from zero and normal device operation will begin. When
RESET is asserted at any time during operation (other than POR), the
counter chain will be cleared.
Real time interrupts (RTI)
The real time interrupt circuit consists of a three stage divider and a
1-of-4 selector. The clock frequency that drives the RTI circuit is f
OP/2
14
(or f
OP/16 384), with three additional divider stages. Register details are
Computer operating properly (COP) watchdog timer
The COP watchdog timer function is implemented by taking the output
of the RTI circuit and further dividing it by eight, as shown in Figure 10.
Note that the minimum COP timeout period is seven times the RTI
period. This is because the COP will be cleared asynchronously with
respect to the value in the core timer counter register/RTI divider, hence
the actual COP timeout period will vary between 7x and 8x the RTI
period.
The COP function is a mask option, enabled or disabled during device
manufacture
. On the MC68HC705E6, the COP function is controlled
using the COP bit in the LVI/options register (see Mask options).
3-ctimer
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