參數(shù)資料
型號: MC68HC705E6VDW
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDSO28
封裝: PLASTIC, SOIC-28
文件頁數(shù): 37/140頁
文件大?。?/td> 1141K
代理商: MC68HC705E6VDW
Glossary
MC68HC05E6 — Rev. 1.0
MOTOROLA
Glossary
131
modulo counter — A counter that can be programmed to count to any number from zero to its
maximum possible modulus.
monitor ROM — A section of ROM that can execute commands from a host computer for testing
purposes.
MOR — See "mask option register (MOR)."
most significant bit (MSB) — The leftmost digit of a binary number.
multiplexer — A device that can select one of a number of inputs and pass the logic level of that
input on to the output.
N — The negative bit in the condition code register of the CPU08. The CPU sets the negative bit
when an arithmetic operation, logical operation, or data manipulation produces a negative
result.
nibble — A set of four bits (half of a byte).
object code — The output from an assembler or compiler that is itself executable machine code,
or is suitable for processing to produce executable machine code.
opcode — A binary code that instructs the CPU to perform an operation.
open-drain — An output that has no pullup transistor. An external pullup device can be
connected to the power supply to provide the logic 1 output voltage.
operand — Data on which an operation is performed. Usually a statement consists of an
operator and an operand. For example, the operator may be an add instruction, and the
operand may be the quantity to be added.
oscillator — A circuit that produces a constant frequency square wave that is used by the
computer as a timing and sequencing reference.
OTPROM — One-time programmable read-only memory. A nonvolatile type of memory that
cannot be reprogrammed.
overflow — A quantity that is too large to be contained in one byte or one word.
page zero — The first 256 bytes of memory (addresses $0000–$00FF).
parity — An error-checking scheme that counts the number of logic 1s in each byte transmitted.
In a system that uses odd parity, every byte is expected to have an odd number of logic
1s. In an even parity system, every byte should have an even number of logic 1s. In the
transmitter, a parity generator appends an extra bit to each byte to make the number of
logic 1s odd for odd parity or even for even parity. A parity checker in the receiver counts
the number of logic 1s in each byte. The parity checker generates an error signal if it finds
a byte with an incorrect number of logic 1s.
相關(guān)PDF資料
PDF描述
MC68HC705E6VDWR3 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDSO28
MC68HC705E6MDWR2 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDSO28
MC68HC05E6MDWR2 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO28
MC68HC05F4FB 8-BIT, MROM, 1.789 MHz, MICROCONTROLLER, PQFP44
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