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參數(shù)資料
| 型號(hào)： | MC68HC705F32 |
| 廠商： | 飛思卡爾半導(dǎo)體(中國(guó))有限公司 |
| 英文描述： | a member of the M68HC05 family of HCMOS |
| 中文描述： | 一對(duì)HCMOS M68HC05系列家庭成員 |
| 文件頁(yè)數(shù)： | 136/198頁(yè) |
| 文件大?。?/td> | 2835K |
| 代理商： | MC68HC705F32 |
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MOTOROLA
14-4
MC68HC05F32
RESETS AND INTERRUPTS
For More Information On This Product,
Go to: www.freescale.com
14.2.1
Interrupt priorities
Each potential interrupt source is assigned a priority which means that if more than one interrupt
is pending at the same time, the processor will service the one with the highest priority first. For
example, if both an external interrupt and a timer interrupt are pending after an instruction
execution, the external interrupt is serviced first.
14.2.2
Non-maskable software interrupt (SWI)
The software interrupt (SWI) is an executable instruction and a nonmaskable interrupt: it is
executed regardless of the state of the I-bit in the CCR. If the I-bit is zero (interrupts enabled), SWI
is executed after interrupts that were pending when the SWI was fetched, but before interrupts
generated after the SWI was fetched. The SWI interrupt service routine address is specified by the
contents of memory locations $FFFC and $FFFD.
14.2.3
Maskable hardware interrupts
If the interrupt mask bit (I-bit) of the CCR is set, all maskable interrupts (internal and external) are
masked. Clearing the I-bit allows interrupt processing to occur. IRQ is software selectable as either
edge or edge-and-level sensitive (bit 3 of the system option register).
Note:
The internal interrupt latch is cleared in the first part of the interrupt service routine;
therefore, one external interrupt pulse could be latched and serviced as soon as the I-bit
is cleared.
14.2.3.1
Real time and core timer (CTIMER) interrupts
There are two different core timer interrupt flags that cause a CTIMER interrupt whenever an
interrupt is enabled and its flag becomes set, namely RTIF and CTOF. The interrupt flags and
enable bits are located in the CTIMER control and status register (CTCSR). These interrupts will
vector to the same interrupt service routine, whose start address is contained in memory locations
$FFF8 and $FFF9 (see
Section 5.2.1
and
Figure 5-1
).
To make use of the real time interrupt the RTIE bit must first be set. The RTIF bit will then be set
after the specified number of counts.
To make use of the core timer overflow interrupt, the CTOFE bit must first be set. The CTOF bit will
then be set when the core timer counter register overflows from $FF to $00.
TPG
130
05F32Book Page 4 Tuesday, June 8, 1999 7:55 am
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
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Freescale Semiconductor, Inc.
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| MC68HC705J1ACDW | 功能描述:IC MCU 4MHZ 1.2K OTP 20-SOIC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:HC05 其它有關(guān)文件:STM32F101T8 View All Specifications 特色產(chǎn)品:STM32 32-bit Cortex MCUs 標(biāo)準(zhǔn)包裝:490 系列:STM32 F1 核心處理器:ARM? Cortex?-M3 芯體尺寸:32-位 速度:36MHz 連通性:I²C，IrDA，LIN，SPI，UART/USART 外圍設(shè)備:DMA，PDR，POR，PVD，PWM，溫度傳感器，WDT 輸入/輸出數(shù):26 程序存儲(chǔ)器容量:64KB（64K x 8） 程序存儲(chǔ)器類型:閃存 EEPROM 大小:- RAM 容量:10K x 8 電壓 - 電源 (Vcc/Vdd):2 V ~ 3.6 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 10x12b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 85°C 封裝/外殼:36-VFQFN，36-VFQFPN 包裝:托盤(pán) 配用:497-10030-ND - STARTER KIT FOR STM32497-8853-ND - BOARD DEMO STM32 UNIV USB-UUSCIKSDKSTM32-PL-ND - KIT IAR KICKSTART STM32 CORTEXM3497-8512-ND - KIT STARTER FOR STM32F10XE MCU497-8505-ND - KIT STARTER FOR STM32F10XE MCU497-8304-ND - KIT STM32 MOTOR DRIVER BLDC497-6438-ND - BOARD EVALUTION FOR STM32 512K497-6289-ND - KIT PERFORMANCE STICK FOR STM32MCBSTM32UME-ND - BOARD EVAL MCBSTM32 + ULINK-MEMCBSTM32U-ND - BOARD EVAL MCBSTM32 + ULINK2更多... 其它名稱:497-9032STM32F101T8U6-ND |
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