參數(shù)資料
型號: MC68HC705J1Ac
廠商: 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述: Microcontrollers
中文描述: 微控制器
文件頁數(shù): 71/162頁
文件大小: 1085K
代理商: MC68HC705J1AC
Resets and Interrupts
Resets
MC68HC705J1A — Rev. 4.0
Technical Data
Resets and Interrupts
4.3.1 Power-On Reset
A positive transition on the V
DD
pin generates a power-on reset.
NOTE:
The power-on reset is strictly for power-up conditions and cannot be
used to detect drops in power supply voltage.
A 4064-t
cyc
(internal clock cycle) delay after the oscillator becomes
active allows the clock generator to stabilize. If any reset source is active
at the end of this delay, the MCU remains in the reset condition until all
reset sources are inactive.
Figure 4-2. Power-On Reset Timing
OSCILLATOR STABILIZATION DELAY
V
DD
OSC1 PIN
INTERNAL
CLOCK
INTERNAL
ADDRESS BUS
Notes:
1. Power-on reset threshold is typically between 1 V and 2 V.
2. Internal clock, internal address bus, and internal data bus are not available externally.
INTERNAL
DATA BUS
$07FE
$07FE
$07FE
$07FE
$07FE
$07FE
$07FF
NEW PCH
NEWPCL
(NOTE 1)
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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