參數(shù)資料
型號： MC68HC705J1AVS
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： Microcontrollers
中文描述： 8-BIT, UVPROM, 2.1 MHz, MICROCONTROLLER, CDIP20
封裝： WINDOWED, CERDIP-20
文件頁數(shù)： 55/108頁
文件大?。?/td> 718K
代理商： MC68HC705J1AVS
Timing
MC68HC705KJ1 MC68HRC705KJ1 MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor
55
The STOP and WAIT instructions set the IRQE bit so that an external interrupt can bring the MCU out of
these low-power modes. In addition, reset sets the I bit which masks all interrupt sources.
5.5 Timing
Figure 5-5. External Interrupt Timing
Table 5-1. External Interrupt Timing (V
DD
= 5.0 Vdc)
(1)
1. V
DD
= 5.0 Vdc
±
10%, V
SS
= 0 Vdc, T
A
= –40
°
C
to + 85
°
C,
unless otherwise noted.
2. t
cyc
= 1/f
OP
; f
OP
= f
OSC
/2.
3. The minimum t
ILIL
should not be less than the number of interrupt service routine cycles plus 19 t
cyc
.
Characteristic
Symbol
Min
Max
Unit
IRQ Interrupt Pulse Width Low (Edge-Triggered)
t
ILIH
1.5
—
t
cyc(2)
IRQ Interrupt Pulse Width
(Edge- and Level-Triggered)
t
ILIH
1.5
Note
(3)
t
cyc
PA0–PA3 Interrupt Pulse Width High (Edge-Triggered)
t
ILIL
1.5
—
t
cyc
PA0–PA3 Interrupt Pulse Width High (Edge- and Level-Triggered)
t
ILIH
1.5
Note
(3)
t
cyc
Table 5-2. External Interrupt Timing (V
DD
= 3.3 Vdc)
(1)
1. V
DD
= 3.3 Vdc
±
10%, V
SS
= 0 Vdc, T
A
= –40
°
C
to + 85
°
C,
unless otherwise noted.
2. t
cyc
= 1/f
OP
; f
OP
= f
OSC
/2.
3. The minimum t
ILIL
should not be less than the number of interrupt service routine cycles plus 19 t
cyc
.
Characteristic
Symbol
Min
Max
Unit
IRQ Interrupt Pulse Width Low (Edge-Triggered)
t
ILIH
1.5
—
t
cyc(2)
IRQ Interrupt Pulse Width
(Edge- and Level-Triggered)
t
ILIH
1.5
Note
(3)
t
cyc
PA0–PA3 Interrupt Pulse Width High (Edge-Triggered)
t
ILIL
1.5
—
t
cyc
PA0–PA3 Interrupt Pulse Width High (Edge- and Level-Triggered)
t
ILIH
1.5
Note
(3)
t
cyc
IRQ (INTERNAL)
t
ILIH
t
ILIL
t
ILIH
IRQ/V
PP
PIN
IRQ
1
.
.
.
IRQ
n
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