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參數(shù)資料
| 型號： | MC68HC705J5ACP |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDIP20 |
| 封裝： | PLASTIC, DIP-20 |
| 文件頁數(shù)： | 72/113頁 |
| 文件大?。?/td> | 1212K |
| 代理商： | MC68HC705J5ACP |
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July 16, 1999
GENERAL RELEASE SPECIFICATION
MC68HC05J5A
16-BIT TIMER
MOTOROLA
REV 2.1
9-3
The timer counter registers (TCNTH, TCNTL) shown in Figure 9-3 are read-only
locations which contain the current high and low bytes of the 16-bit free-running
counter. Writing to the timer registers has no effect. Reset of the device presets
the timer counter to $FFFC.
The TCNTL latch is a transparent read of the LSB until the a read of the TCNTH
takes place. A read of the TCNTH latches the LSB into the TCNTL location until
the TCNTL is again read. The latched value remains xed even if multiple reads of
the TCNTH take place before the next read of the TCNTL. Therefore, when read-
ing the MSB of the timer at TCNTH the LSB of the timer at TCNTL must also be
read to complete the read sequence.
During power-on-reset (POR), the counter is initialized to $FFFC and begins
counting after the oscillator start-up delay. Because the counter is 16 bits and pre-
ceded by a xed divide-by-four prescaler, the value in the counter repeats every
262, 144 internal bus clock cycles (524, 288 oscillator cycles).
When the free-running counter rolls over from $FFFF to $0000, the timer overow
ag bit (T1OF) is set in the T1SR. When the T1OF is set, it can generate an inter-
rupt if the timer overow interrupt enable bit (T1OIE) is also set in the T1CR. The
T1OF ag bit can only be reset by reading the TCNTL after reading the T1SR.
Other than clearing any possible T1OF ags, reading the TCNTH and TCNTL in
any order or any number of times does not have any effect on the 16-bit free-run-
ning counter.
NOTE
To prevent interrupts from occurring between readings of the TCNTH and TCNTL,
set the I bit in the condition code register (CCR) before reading TCNTH and clear
the I bit after reading TCNTL.
9.2
ALTERNATE COUNTER REGISTERS (ACNTH, ACNTL)
The functional block diagram of the 16-bit free-running timer counter and alternate
counter registers is shown in Figure 9-4. The alternate counter registers behave
the same as the timer counter registers, except that any reads of the alternate
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
TCNTH
R
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
$0018
W
reset:
11111111
TCNTL
R
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
$0019
W
reset:
11111100
Figure 9-3. 16-Bit Timer Counter Registers (TCNTH, TCNTL)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC68HC705JB4DW | 制造商:Motorola Inc 功能描述: 制造商:MOTOROLA 功能描述: |
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| MC68HC705JP7CDW | 功能描述:IC MCU 8BIT 28-SOIC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:HC05 其它有關(guān)文件:STM32F101T8 View All Specifications 特色產(chǎn)品:STM32 32-bit Cortex MCUs 標(biāo)準(zhǔn)包裝:490 系列:STM32 F1 核心處理器:ARM? Cortex?-M3 芯體尺寸:32-位 速度:36MHz 連通性:I²C，IrDA，LIN，SPI，UART/USART 外圍設(shè)備:DMA，PDR，POR，PVD，PWM，溫度傳感器，WDT 輸入/輸出數(shù):26 程序存儲器容量:64KB（64K x 8） 程序存儲器類型:閃存 EEPROM 大小:- RAM 容量:10K x 8 電壓 - 電源 (Vcc/Vdd):2 V ~ 3.6 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 10x12b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 85°C 封裝/外殼:36-VFQFN，36-VFQFPN 包裝:托盤 配用:497-10030-ND - STARTER KIT FOR STM32497-8853-ND - BOARD DEMO STM32 UNIV USB-UUSCIKSDKSTM32-PL-ND - KIT IAR KICKSTART STM32 CORTEXM3497-8512-ND - KIT STARTER FOR STM32F10XE MCU497-8505-ND - KIT STARTER FOR STM32F10XE MCU497-8304-ND - KIT STM32 MOTOR DRIVER BLDC497-6438-ND - BOARD EVALUTION FOR STM32 512K497-6289-ND - KIT PERFORMANCE STICK FOR STM32MCBSTM32UME-ND - BOARD EVAL MCBSTM32 + ULINK-MEMCBSTM32U-ND - BOARD EVAL MCBSTM32 + ULINK2更多... 其它名稱:497-9032STM32F101T8U6-ND |
| MC68HC705JP7CP | 制造商:Rochester Electronics LLC 功能描述: 制造商:Freescale Semiconductor 功能描述: |
| MC68HC705K1CDW | 制造商:Motorola Inc 功能描述: |
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