參數(shù)資料
型號(hào)： MC68HC705J5ACP
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDIP20
封裝： PLASTIC, DIP-20
文件頁(yè)數(shù)： 37/106頁(yè)
文件大?。?/td> 1419K
代理商： MC68HC705J5ACP
GENERAL RELEASE SPECIFICATION
July 16, 1999
RESETS
MC68HC05J5A
5-2
REV 2.1
5.1
EXTERNAL RESET (RESET)
The RESET pin is the only external source of a reset. This pin is connected to a
Schmitt trigger input gate to provide an upper and lower threshold voltage sepa-
rated by a minimum amount of hysteresis. This external reset occurs whenever
the RESET pin is pulled below the lower threshold and remains in reset until the
RESET pin rises above the upper threshold. This active low input will generate the
RST signal and reset the CPU and peripherals. This pin is also an output pin
whenever the LVR triggers an internal reset. Termination of the external RESET
input or the internal COP Watchdog reset or LVR are the only reset sources that
can alter the operating mode of the MCU.
NOTE
Activation of the RST signal is generally referred to as reset of the device, unless
otherwise specied.
5.2
INTERNAL RESETS
The four internally generated resets are the initial power-on reset function, the
COP Watchdog Timer reset, the illegal address detector reset and the low voltage
reset (LVR). Termination of the external RESET input or the internal COP Watch-
dog Timer or LVR are the only reset sources that can alter the operating mode of
the MCU. The other internal resets will not have any effect on the mode of opera-
tion when their reset state ends.
5.2.1 POWER-ON RESET (POR)
The internal POR is generated on power-up to allow the clock oscillator to stabi-
lize. The POR is strictly for power turn-on conditions and is not able to detect a
drop in the power supply voltage (brown-out). There is an oscillator stabilizing
delay after the oscillator becomes active. The delay time could be 224 or 4064 of
internal processor bus clock cycles (PH2) which is a mask option.
The POR will generate the RST signal which will reset the CPU. If any other reset
function is active at the end of this delay time, the RST signal will remain in the
reset condition until the other reset condition(s) end.
5.2.2 COMPUTER OPERATING PROPERLY RESET (COPR)
The internal COPR reset is generated automatically (if the COP is enabled) by a
time-out of the COP Watchdog Timer. This time-out occurs if the counter in the
COP Watchdog Timer is not reset (cleared) within a specic time by a software
reset sequence. The COP Watchdog Timer can be disabled by a mask option.
Refer to Section 8.2 for more information on this time-out feature. COP reset also
forces the RESET pin low
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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相關(guān)PDF資料
PDF描述
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MC68HRC705J5ACP 8-BIT, OTPROM, MICROCONTROLLER, PDIP20
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