參數(shù)資料
型號： MC68HC705KJ1CDWR2
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 4 MHz, MICROCONTROLLER, PDSO16
封裝： SOIC-16
文件頁數(shù)： 14/144頁
文件大?。?/td> 1377K
代理商： MC68HC705KJ1CDWR2
Technical Data
MC68HC705KJ1 — Rev. 2.0
110
Multifunction Timer Module
MOTOROLA
Multifunction Timer Module
interrupt request to be generated. To prevent this occurrence, clear the
COP timer before changing RT1 and RT0.
10.6.2 Timer Counter Register
A 15-stage ripple counter is the core of the timer. The value of the first
eight stages is readable at any time from the read-only timer counter
register shown in Figure 10-4.
Power-on clears the entire counter chain and the internal clock begins
clocking the counter. After 4064 cycles (or 16 cycles if the SOSCD bit in
the mask option register is set), the power-on reset circuit is released,
clearing the counter again and allowing the MCU to come out of reset.
A timer overflow function at the eighth counter stage allows a timer
interrupt every 1024 internal clock cycles.
Table 10-2. Real-Time Interrupt Rate Selection
RT1:RT0
RTI
Rate
RTI Period
(fOP =
2 MHz)
COP Timeout
Period
(–0/+1 RTI Period)
Minimum COP
Timeout Period
(fOP = 2 MHz)
00
fOP ÷ 2
14
8.2 ms
8 x RTI Period
65.5 ms
01
fOP ÷ 2
15
16.4 ms
8 x RTI Period
131.1 ms
10
fOP ÷ 2
16
32.8 ms
8 x RTI Period
262.1 ms
11
fOP ÷ 2
17
65.5 ms
8 x RTI Period
524.3 ms
Address:
$0009
Bit 7
654321
Bit 0
Read:
TCR7
TCR6
TCR5
TCR4
TCR3
TCR2
TCR1
TCR0
Write:
Reset:
00000000
= Unimplemented
Figure 10-4. Timer Counter Register (TCR)
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