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參數(shù)資料
| 型號： | MC68HC705L28B |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | NPN Epitaxial Silicon Transistor |
| 中文描述： | 8-BIT, OTPROM, 2.17 MHz, MICROCONTROLLER, PDIP56 |
| 封裝： | PLASTIC, SHRINK, DIP-56 |
| 文件頁數(shù)： | 40/108頁 |
| 文件大?。?/td> | 718K |
| 代理商： | MC68HC705L28B |
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Central Processor Unit (CPU)
MC68HC705KJ1 MC68HRC705KJ1 MC68HLC705KJ1 Data Sheet, Rev. 4.1
40
Freescale Semiconductor
4.6.2.2 Read-Modify-Write Instructions
These instructions read a memory location or a register, modify its contents, and write the modified value
back to the memory location or to the register.
NOTE
Do not use read-modify-write instructions on registers with write-only bits.
4.6.2.3 Jump/Branch Instructions
Jump instructions allow the CPU to interrupt the normal sequence of the program counter. The
unconditional jump instruction (JMP) and the jump-to-subroutine instruction (JSR) have no register
operand. Branch instructions allow the CPU to interrupt the normal sequence of the program counter
when a test condition is met. If the test condition is not met, the branch is not performed.
The BRCLR and BRSET instructions cause a branch based on the state of any readable bit in the first
256 memory locations. These 3-byte instructions use a combination of direct addressing and relative
addressing. The direct address of the byte to be tested is in the byte following the opcode. The third byte
is the signed offset byte. The CPU finds the effective branch destination by adding the third byte to the
program counter if the specified bit tests true. The bit to be tested and its condition (set or clear) is part of
the opcode. The span of branching is from –128 to +127 from the address of the next location after the
Table 4-2. Read-Modify-Write Instructions
Instruction
Mnemonic
Arithmetic Shift Left (Same as LSL)
ASL
Arithmetic Shift Right
ASR
Bit Clear
BCLR
(1)
1. Unlike other read-modify-write instructions, BCLR and
BSET use only direct addressing.
2. TST is an exception to the read-modify-write sequence
because it does not write a replacement value.
Bit Set
BSET
(1)
Clear Register
CLR
Complement (One’s Complement)
COM
Decrement
DEC
Increment
INC
Logical Shift Left (Same as ASL)
LSL
Logical Shift Right
LSR
Negate (Two’s Complement)
NEG
Rotate Left through Carry Bit
ROL
Rotate Right through Carry Bit
ROR
Test for Negative or Zero
TST
(2)
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| MC68HC705L32FU | 制造商:Rochester Electronics LLC 功能描述: 制造商:Freescale Semiconductor 功能描述: |
| MC68HC705L5FUE | 功能描述:8位微控制器 -MCU 705L5-EPP-80QFP-6019 RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
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| MC68HC705P6ACDW | 功能描述:8位微控制器 -MCU 8 Bit 2.1MHz RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| MC68HC705P6ACP | 功能描述:IC MCU 2.1MHZ 4.5K OTP 28-DIP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:HC05 其它有關(guān)文件:STM32F101T8 View All Specifications 特色產(chǎn)品:STM32 32-bit Cortex MCUs 標準包裝:490 系列:STM32 F1 核心處理器:ARM? Cortex?-M3 芯體尺寸:32-位 速度:36MHz 連通性:I²C，IrDA，LIN，SPI，UART/USART 外圍設(shè)備:DMA，PDR，POR，PVD，PWM，溫度傳感器，WDT 輸入/輸出數(shù):26 程序存儲器容量:64KB（64K x 8） 程序存儲器類型:閃存 EEPROM 大小:- RAM 容量:10K x 8 電壓 - 電源 (Vcc/Vdd):2 V ~ 3.6 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 10x12b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 85°C 封裝/外殼:36-VFQFN，36-VFQFPN 包裝:托盤 配用:497-10030-ND - STARTER KIT FOR STM32497-8853-ND - BOARD DEMO STM32 UNIV USB-UUSCIKSDKSTM32-PL-ND - KIT IAR KICKSTART STM32 CORTEXM3497-8512-ND - KIT STARTER FOR STM32F10XE MCU497-8505-ND - KIT STARTER FOR STM32F10XE MCU497-8304-ND - KIT STM32 MOTOR DRIVER BLDC497-6438-ND - BOARD EVALUTION FOR STM32 512K497-6289-ND - KIT PERFORMANCE STICK FOR STM32MCBSTM32UME-ND - BOARD EVAL MCBSTM32 + ULINK-MEMCBSTM32U-ND - BOARD EVAL MCBSTM32 + ULINK2更多... 其它名稱:497-9032STM32F101T8U6-ND |
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