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參數(shù)資料
| 型號： | MC68HC705V12 |
| 廠商： | Motorola, Inc. |
| 英文描述： | The Motorola microcontroller |
| 中文描述： | 摩托羅拉單片機 |
| 文件頁數(shù)： | 73/108頁 |
| 文件大?。?/td> | 718K |
| 代理商： | MC68HC705V12 |
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Interrupts
MC68HC705KJ1 MC68HRC705KJ1 MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor
73
8.2.3 COP Watchdog Reset
A timeout of the COP watchdog generates a COP reset. The COP watchdog is part of a software error
detection system and must be cleared periodically to start a new timeout period. To clear the COP
watchdog and prevent a COP reset, write a logic 0 to bit 0 (COPC) of the COP register at location $07F0.
8.2.4 Illegal Address Reset
An opcode fetch from an address not in RAM or EPROM generates a reset.
8.3 Interrupts
The following sources can generate interrupts:
SWI instruction
External interrupt pins
–
IRQ/V
PP
pin
–
PA0–PA3 pins
Timer
–
Real-time interrupt flag (RTIF)
–
Timer overflow flag (TOF)
An interrupt temporarily stops the program sequence to process a particular event. An interrupt does not
stop the operation of the instruction being executed, but takes effect when the current instruction
completes its execution. Interrupt processing automatically saves the CPU registers on the stack and
loads the program counter with a user-defined interrupt vector address.
8.3.1 Software Interrupt
The software interrupt (SWI) instruction causes a non-maskable interrupt.
8.3.2 External Interrupt
An interrupt signal on the IRQ/V
PP
pin latches an external interrupt request. When the CPU completes its
current instruction, it tests the IRQ latch. If the IRQ latch is set, the CPU then tests the I bit in the condition
code register. If the I bit is clear, the CPU then begins the interrupt sequence.
The CPU clears the IRQ latch during interrupt processing, so that another interrupt signal on the IRQ/V
PP
pin can latch another interrupt request during the interrupt service routine. As soon as the I bit is cleared
during the return from interrupt, the CPU can recognize the new interrupt request.
Figure 8-4
shows the
IRQ/V
PP
pin interrupt logic.
Setting the I bit in the condition code register disables external interrupts.
The port A external interrupt bit (PIRQ) in the mask option register enables pins PA0–PA3 to function as
external interrupt pins.
The external interrupt sensitivity bit (LEVEL) in the mask option register controls interrupt triggering
sensitivity of external interrupt pins. The IRQ/V
PP
pin can be negative-edge triggered only or
negative-edge and low-level triggered. Port A external interrupt pins can be positive-edge triggered only
or both positive-edge and high-level triggered. The level-sensitive triggering option allows multiple
external interrupt sources to be wire-ORed to an external interrupt pin. An external interrupt request,
shown in
Figure 8-5
, is latched as long as any source is holding an external interrupt pin low.
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