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| 型號： | MC68HC705X4 |
| 廠商： | Motorola, Inc. |
| 英文描述： | HCMOS Microcontroller Unit |
| 中文描述： | HCMOS微控制器 |
| 文件頁數(shù)： | 52/156頁 |
| 文件大?。?/td> | 926K |
| 代理商： | MC68HC705X4 |
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Resets, Interrupts and Low Power Modes
MC68HC05X4
52
Resets, Interrupts and Low Power Modes
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
WOI interrupt is bit 5 of the port configuration register ($03). This latch is
set by the WOI, and is cleared by writing a zero to the bit. A WOI will
cause the MPU to exit from STOP mode.
Real time and
core timer
(C TIMER) interrupts
There are two different core timer interrupt flags that cause a CTIMER
interrupt whenever an interrupt is enabled and its flag becomes set,
namely RTIF and CTOF. The interrupt flags and enable bits are located
in the CTIMER control and status register (CTCSR). These interrupts will
vector to the same interrupt service routine, whose start address is
contained in memory locations $1FF8 and $1FF9 (see
Core timer
control and status register (CTCSR)
and
Figure 1
).
To make use of the real time interrupt the RTIE bit must first be set. The
RTIF bit will then be set after the specified number of counts.
To make use of the core timer overflow interrupt the CTOFE bit must first
be set. The CTOF bit will then be set when the core timer counter
register overflows from $FF to $00.
Programmable
16-bit timer
interrupt
There are three different timer interrupt flags (ICF, OCF, TOF) that
cause a timer interrupt whenever they are set and enabled. The timer
interrupt enable bits (ICIE, OCIE, TOIE) are located in the timer control
register (TCR) and the timer interrupt flag is located in the timer status
register (TSR). All three interrupts will vector to the same service routine,
whose start address is contained in memory locations $1FF4 and
$1FF5.
Hardware
controlled
interrupt
sequence
The following three functions (RESET, STOP, and WAIT) are not in the
strictest sense interrupts. However, they are acted upon in a similar
manner. Flowcharts for STOP and WAIT are shown in
Figure 3
.
RESET:
A reset condition causes the program to vector to its
starting address, which is contained in memory locations
$1FFE (MSB) and $1FFF (LSB). The I-bit in the condition
code register is also set, to disable interrupts.
STOP:
The STOP instruction causes the oscillator to be turned off
and the processor to ‘sleep’ until an external interrupt
6-resets
F
Freescale Semiconductor, Inc.
n
.
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