參數(shù)資料
型號： MC68HC705X4DW
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： HCMOS Microcontroller Unit
中文描述： 8-BIT, OTPROM, 2.2 MHz, MICROCONTROLLER, PDSO28
封裝： SOIC-28
文件頁數(shù)： 65/156頁
文件大小： 926K
代理商： MC68HC705X4DW
Parallel input/output ports
Port B
MC68HC05X4 Rev 1.0
MOTOROLA
Parallel input/output ports
For More Information On This Product,
Go to: www.freescale.com
65
WOI enable and pull-down enable registers control each pin individually;
these registers are memory mapped to the same addresses as port A
data register and data direction register (i.e $00 and $04). When the
AWPS bit in the port configuration register (PCR) is set, port A WOI
enable and pull-down enable registers are selected instead of port A
data and DDR registers. Data and DDR registers are selected when the
AWPS bit in PCR is cleared; this is also cleared at reset. Note that WOI
can be programmed independently of the DDR contents (input or
output).
Port B
Port B is an 8-bit bi-directional port. The port B data register is at $0001
and the data direction register (DDR) is at $0005. Reset does not affect
the data register, but clears the data direction register, thereby returning
the ports to inputs. Writing a ‘1’ to a DDR bit sets the corresponding port
bit to output mode. On port B a single WOI enable bit and a single
pull-down enable bit are provided to control all 8 bits together. These two
bits are respectively bit 1 and bit 2 of port configuration register (PCR).
When bit 1 of the PCR is set, WOI is enabled only on those port B pins
that have been programmed as inputs. Note that port B shares pin 1 of
the device with the TCMP function of the 16-bit programmable timer. If
bit 4 of the PCR is set then pin 1 is TCMP and the wired-OR functions
are disabled on this pin. If bit 4 in the PCR is ‘0’ then pin 1 is PB7. On
reset, bits 0–4 of the PCR are cleared.
Table 1. I/O pin functions
R/W
DDR
I/O pin function
0
0
The I/O pin is in input mode. Data is written into the output data latch.
0
1
Data is written into the output data latch, and output to the I/O pin.
1
0
The state of the I/O pin is read.
1
1
The I/O pin is in output mode. The output data latch is read.
Note that R/W is an internal signal, not available to the user.
3-ports
F
Freescale Semiconductor, Inc.
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