參數(shù)資料
型號： MC68HC805P18DWR3
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, EEPROM, MICROCONTROLLER, PDSO28
封裝： SOIC-28
文件頁數(shù)： 138/144頁
文件大小： 1348K
代理商： MC68HC805P18DWR3
16-Bit Timer
Input Capture
MC68HC(8)05P18 — Rev. 2.0
Advance Information
MOTOROLA
16-Bit Timer
93
The contents of the free-running counter are transferred to the input
capture registers on each proper signal transition regardless of the state
of the input capture flag bit (ICF) in register TSR. The input capture
registers always contain the free-running counter value which
corresponds to the most recent input capture.
After a read of the MSB of the input capture register pair (ICRH), counter
transfers are inhibited until the LSB of the register pair (ICRL) is also
read. This characteristic forces the minimum pulse period attainable to
be determined by the time required to execute an input capture software
routine in an application.
Reading the LSB of the input capture register pair (ICRL) does not inhibit
transfer of the free-running counter. Again, minimum pulse periods are
ones which allow software to read the LSB of the register pair (ICRL) and
perform needed operations. There is no conflict between reading the
LSB (ICRL) and the free-running counter transfer, since they occur on
opposite edges of the PH2 clock.
Register name and address: ICRH — $0014
Bit 7
654321
Bit 0
Read:
ICRH7
ICRH6
ICRH5
ICRH4
ICRH3
ICRH2
ICRH1
ICRH0
Write:
Reset:
Unaffected by reset
Register name and address: ICRL — $0015
Bit 7
654321
Bit 0
Read:
ICRL7
ICRL6
ICRL5
ICRL4
ICRL3
ICRL2
ICRL1
ICRL0
Write:
Reset:
Unaffected by reset
= Unimplemented
Figure 10-8. Input Capture Registers (ICRH/ICRL)
相關(guān)PDF資料
PDF描述
MC68HC805P18CDWR2 8-BIT, EEPROM, MICROCONTROLLER, PDSO28
MC68HC805P18MDWR2 8-BIT, EEPROM, MICROCONTROLLER, PDSO28
MC68HC05P18CP 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP28
MC68HC05P18MP 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP28
MC68HC05P18MDW 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO28
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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