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參數(shù)資料
| 型號(hào)： | MC68HC805P18MDWR2 |
| 廠商： | MOTOROLA INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, EEPROM, MICROCONTROLLER, PDSO28 |
| 封裝： | SOIC-28 |
| 文件頁(yè)數(shù)： | 116/144頁(yè) |
| 文件大?。?/td> | 1348K |
| 代理商： | MC68HC805P18MDWR2 |
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EEPROM
EEPROM Programming Register
MC68HC(8)05P18 — Rev. 2.0
Advance Information
MOTOROLA
EEPROM
73
In byte erase mode, only the selected byte is erased. In block mode,
a 32-byte block of EEPROM is erased. The EEPROM memory space
is divided into four 32-byte blocks ($140–$15F, $160–$17F,
$180–$19F and $1A0–$1BF) and doing a block erase to any address
within a block will erase the entire block. In bulk erase mode, the
entire 128-byte EEPROM section is erased.
LATCH — Latch Bit
When set, LATCH configures the EEPROM address and data bus for
programming. Writes to the EEPROM array cause the data bus and
the address bus to be latched. This bit is readable and writable, but
reads from the array are inhibited if the LATCH bit is set and a write
to the EEPROM space has taken place.
When clear, address and data buses are configured for normal
operation. Reset clears this bit.
EERC — EEPROM RC Oscillator Control Bit
When this bit is set, the EEPROM section uses the internal RC
oscillator instead of the CPU clock. The RC oscillator is shared with
the A/D converter, so this bit should be set by the user when the
internal bus frequency is below 1.5 MHz to guarantee reliable
operation of the EEPROM or A/D converter. After setting the EERC
bit, delay a time, tRCON, to allow the RC oscillator to stabilize. This bit
is readable and writable. The EERC bit is cleared by reset. The RC
oscillator is disabled while the MCU is in stop mode.
EEPGM — EEPROM Programming Power Enable Bit
EEPGM must be written to enable (or disable) the EEPGM function.
When set, EEPGM turns on the charge pump and enables the
programming (or erasing) power to the EEPROM array. When clear,
this power is switched off. This will enable pulsing of the programming
voltage to be controlled internally. This bit can be read at any time, but
can only be written to if LATCH = 1. If LATCH is not set, then EEPGM
cannot be set. LATCH and EEPGM cannot both be set with one write
if LATCH is cleared. EEPGM is cleared automatically when LATCH is
cleared. Reset clears this bit.
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