Serial Communications Interface (SCI)
Data Sheet
M68HC11E Family — Rev. 5
128
Serial Communications Interface (SCI)
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MOTOROLA
SCR[2:0] — SCI Baud Rate Select Bits
Selects receiver and transmitter bit rate based on output from baud rate
prescaler stage. Refer to
Figure 7-8
and
Figure 7-9
.
The prescaler bits, SCP[2:0], determine the highest baud rate, and the SCR[2:0]
bits select an additional binary submultiple (
÷
1,
÷
2,
÷
4, through
÷
128) of this
highest baud rate. The result of these two dividers in series is the 16X receiver
baud rate clock. The SCR[2:0] bits are not affected by reset and can be changed
at any time, although they should not be changed when any SCI transfer is in
progress.
Figure 7-8
and
Figure 7-9
illustrate the SCI baud rate timing chain. The
prescaler select bits determine the highest baud rate. The rate select bits
determine additional divide by two stages to arrive at the receiver timing (RT)
clock rate. The baud rate clock is the result of dividing the RT clock by 16.
Figure 7-8. SCI Baud Rate Generator Block Diagram
0:0:0
÷
2
0:0:1
÷
2
0:1:0
÷
2
0:1:1
÷
2
1:0:0
÷
2
1:0:1
÷
2
1:1:0
÷
2
SCI
TRANSMIT
BAUD RATE
(1X)
SCI
RECEIVE
BAUD RATE
(16X)
÷
16
1:1:1
SCR[2:0]
÷
3
0:0
÷
4
÷
13
0:1
1:0
1:1
OSCILLATOR
AND
CLOCK GENERATOR
(
÷
4)
SCP[1:0]
INTERNAL BUS CLOCK (PH2)
E
AS
EXTAL
XTAL
F
Freescale Semiconductor, Inc.
n
.