參數(shù)資料
型號(hào)： MC68HC901P
廠商： MOTOROLA INC
元件分類(lèi)： 外設(shè)及接口
英文描述： Multi-Function Peripheral
中文描述： MULTIFUNCTION PERIPHERAL, PDIP48
封裝： PLASTIC, DIP-48
文件頁(yè)數(shù)： 41/73頁(yè)
文件大?。?/td> 274K
代理商： MC68HC901P
Timers
6-4
MC68HC901 USER’S MANUAL
MOTOROLA
The active edge of the auxiliary input signal is defined by the associated channel's edge bit.
GPIP4 of the AER specifies the active edge for TAI, and GPIP3 defines the active edge for
TBI. When the edge bit is programmed to a one, a count pulse will be generated on the zero-
to-one transition of the auxiliary input signal. When the edge bit is programmed to a zero, a
count pulse will be generated on the one-to-zero transition. Also, note that changing the
state of the edge bit while the timer is in the event count mode may produce a count pulse.
6.2 TIMER REGISTERS
The four timers are programmed via three control registers and four data registers. The
following paragraphs describe the different registers.
6.2.1 Timer Data Registers (TxDR)
The four timer data registers (TDRs) are designated as Timer A data register (TADR), Timer
B data register (TBDR), Timer C data register (TCDR), and Timer D data register (TDDR).
Each timer's main counter is an 8-bit binary down counter. The timer data registers contain
the value of their respective main counter. This value was captured on the last low-to-high
transition of the data strobe pin.
The main counter is initialized by writing to the TDR. If the timer is stopped, data is loaded
simultaneously into both the TDR and main counter. If the TDR is written to while the timer
is enabled, the value is not loaded into the timer until the timer counts through 01
(hexadecimal). If a write is performed while the timer is counting through 01, then an
indeterminate value will be loaded into the timer's main counter.
D7-D0 — Data
0 = Cleared.
1 = Set.
6.2.2 Timer Control Registers (TxCR)
Timer A control register (TACR) and timer B control register (TBCR) are associated with
timers A and B, respectively. Timers C and D are programmed using one control register—
the timer C and D control register (TCDCR). The bits in the control register select the
operation mode, prescaler value, and disable the timers. Both control registers have bits
which allow the programmer to reset output lines TA0 and TB0.
TxDR REGISTER
BIT
7
6
5
4
3
2
1
0
FIELD
D7
D6
D5
D4
D3
D2
D1
D0
RESET
0
0
0
0
0
0
0
0
ADDR
$1F, $21, $23, $25
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