參數(shù)資料
型號(hào): MC68HC908AS32AVFUE
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 8.4 MHz, MICROCONTROLLER, PQFP64
封裝: 14 X 14 MM, GREEN, PLASTIC, QFP-64
文件頁(yè)數(shù): 147/280頁(yè)
文件大?。?/td> 1967K
代理商: MC68HC908AS32AVFUE
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Timer Interface Module (TIM)
MC68HC908AS32A Data Sheet, Rev. 2.0
230
Freescale Semiconductor
17.3.2 Input Capture
An input capture function has three basic parts: edge select logic, an input capture latch, and a 16-bit
counter. Two 8-bit registers, which make up the 16-bit input capture register, are used to latch the value
of the free-running counter after the corresponding input capture edge detector senses a defined
transition. The polarity of the active edge is programmable. The level transition which triggers the counter
transfer is defined by the corresponding input edge bits (ELSxB and ELSxA in TSC0–TSC5 control
registers with x referring to the active channel number). When an active edge occurs on the pin of an input
capture channel, the TIM latches the contents of the TIM counter into the TIM channel registers,
TCHxH–TCHxL. Input captures can generate TIM CPU interrupt requests. Software can determine that
an input capture event has occurred by enabling input capture interrupts or by polling the status flag bit.
The free-running counter contents are transferred to the TIM channel register (TCHxH–TCHxL see 17.8.5
TIM Channel Registers) on each proper signal transition regardless of whether the TIM channel flag
(CH0F–CH5F in TSC0–TSC5 registers) is set or clear. When the status flag is set, a CPU interrupt is
generated if enabled. The value of the count latched or “captured” is the time of the event. Because this
value is stored in the input capture register 2 bus cycles after the actual event occurs, user software can
respond to this event at a later time and determine the actual time of the event. However, this must be
done prior to another input capture on the same pin; otherwise, the previous time value will be lost.
By recording the times for successive edges on an incoming signal, software can determine the period
and/or pulse width of the signal. To measure a period, two successive edges of the same polarity are
captured. To measure a pulse width, two alternate polarity edges are captured. Software should track the
overflows at the 16-bit module counter to extend its range.
Another use for the input capture function is to establish a time reference. In this case, an input capture
function is used in conjunction with an output compare function. For example, to activate an output signal
a specified number of clock cycles after detecting an input event (edge), use the input capture function to
record the time at which the edge occurred. A number corresponding to the desired delay is added to this
captured value and stored to an output compare register (see 17.8.5 TIM Channel Registers). Because
both input captures and output compares are referenced to the same 16-bit modulo counter, the delay
can be controlled to the resolution of the counter independent of software latencies.
Reset does not affect the contents of the TIM channel registers.
17.3.3 Output Compare
With the output compare function, the TIM can generate a periodic pulse with a programmable polarity,
duration, and frequency. When the counter reaches the value in the registers of an output compare
channel, the TIM can set, clear or toggle the channel pin. Output compares can generate TIM CPU
interrupt requests.
17.3.3.1 Unbuffered Output Compare
Any output compare channel can generate unbuffered output compare pulses as described in 17.3.3
Output Compare. The pulses are unbuffered because changing the output compare value requires writing
the new value over the old value currently in the TIM channel registers.
An unsynchronized write to the TIM channel registers to change an output compare value could cause
incorrect operation for up to two counter overflow periods. For example, writing a new value before the
counter reaches the old value but after the counter reaches the new value prevents any compare during
that counter overflow period. Also, using a TIM overflow interrupt routine to write a new, smaller output
compare value may cause the compare to be missed. The TIM may pass the new value before it is written.
相關(guān)PDF資料
PDF描述
MC68HC908AS32AMFNE 8-BIT, FLASH, 8.4 MHz, MICROCONTROLLER, PQCC52
MC68HC908AS32AVFNE 8-BIT, FLASH, 8.4 MHz, MICROCONTROLLER, PQCC52
MC68HC908AS32AVFN 8-BIT, FLASH, 8.4 MHz, MICROCONTROLLER, PQCC52
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