
System Integration Module (SIM)
Data Sheet
MC68HC908GR60A MC68HC908GR48A MC68HC908GR32A
208
System Integration Module (SIM)
MOTOROLA
14.3.2 Active Resets from Internal Sources
All internal reset sources actively pull the RST pin low for 32 CGMXCLK cycles to
allow resetting of external peripherals. The internal reset continues to be asserted
for an additional 32 cycles at which point the reset vector will be fetched. See
Figure 14-5. An internal reset can be caused by an illegal address, illegal opcode,
NOTE:
For LVI or POR resets, the SIM cycles through 4096 CGMXCLK cycles during
which the SIM forces the RST pin low. The internal reset signal then follows the
sequence from the falling edge of RST shown in Figure 14-5.
The COP reset is asynchronous to the bus clock.
The active reset feature allows the part to issue a reset to peripherals and other
chips within a system built around the MCU.
Figure 14-5. Internal Reset Timing
Figure 14-6. Sources of Internal Reset
Table 14-2. Reset Recovery
Reset Recovery Type
Actual Number of Cycles
POR/LVI
4163 (4096 + 64 + 3)
All others
67 (64 + 3)
RST
RSTPULLEDLOWBYMCU
IAB
32 CYCLES
VECTOR HIGH
CGMXCLK
ILLEGAL ADDRESS RST
ILLEGAL OPCODE RST
COPRST
LVI
POR
INTERNAL RESET
MODRST