參數(shù)資料
型號(hào): MC68HC908GR4CFAE
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 8.2 MHz, MICROCONTROLLER, PQFP32
封裝: 7 X 7 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, MS-026BBA, LQFP-32
文件頁(yè)數(shù): 92/286頁(yè)
文件大?。?/td> 3708K
代理商: MC68HC908GR4CFAE
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I/O Registers
MC68HC908GR8 MC68HC908GR4 Data Sheet, Rev. 7
Freescale Semiconductor
181
IDLE — Receiver Idle Bit
This clearable, read-only bit is set when 10 or 11 consecutive logic 1s appear on the receiver input.
IDLE generates an SCI receiver CPU interrupt request if the ILIE bit in SCC2 is also set. Clear the IDLE
bit by reading SCS1 with IDLE set and then reading the SCDR. After the receiver is enabled, it must
receive a valid character that sets the SCRF bit before an idle condition can set the IDLE bit. Also, after
the IDLE bit has been cleared, a valid character must again set the SCRF bit before an idle condition
can set the IDLE bit. Reset clears the IDLE bit.
1 = Receiver input idle
0 = Receiver input active (or idle since the IDLE bit was cleared)
OR — Receiver Overrun Bit
This clearable, read-only bit is set when software fails to read the SCDR before the receive shift
register receives the next character. The OR bit generates an SCI error CPU interrupt request if the
ORIE bit in SCC3 is also set. The data in the shift register is lost, but the data already in the SCDR is
not affected. Clear the OR bit by reading SCS1 with OR set and then reading the SCDR. Reset clears
the OR bit.
1 = Receive shift register full and SCRF = 1
0 = No receiver overrun
Software latency may allow an overrun to occur between reads of SCS1 and SCDR in the flag-clearing
sequence. Figure 18-13 shows the normal flag-clearing sequence and an example of an overrun
caused by a delayed flag-clearing sequence. The delayed read of SCDR does not clear the OR bit
because OR was not set when SCS1 was read. Byte 2 caused the overrun and is lost. The next
flag-clearing sequence reads byte 3 in the SCDR instead of byte 2.
In applications that are subject to software latency or in which it is important to know which byte is lost
due to an overrun, the flag-clearing routine can check the OR bit in a second read of SCS1 after
reading the data register.
NF — Receiver Noise Flag Bit
This clearable, read-only bit is set when the SCI detects noise on the PE1/RxD pin. NF generates an
NF CPU interrupt request if the NEIE bit in SCC3 is also set. Clear the NF bit by reading SCS1 and
then reading the SCDR. Reset clears the NF bit.
1 = Noise detected
0 = No noise detected
FE — Receiver Framing Error Bit
This clearable, read-only bit is set when a logic 0 is accepted as the stop bit. FE generates an SCI error
CPU interrupt request if the FEIE bit in SCC3 also is set. Clear the FE bit by reading SCS1 with FE set
and then reading the SCDR. Reset clears the FE bit.
1 = Framing error detected
0 = No framing error detected
PE — Receiver Parity Error Bit
This clearable, read-only bit is set when the SCI detects a parity error in incoming data. PE generates
a PE CPU interrupt request if the PEIE bit in SCC3 is also set. Clear the PE bit by reading SCS1 with
PE set and then reading the SCDR. Reset clears the PE bit.
1 = Parity error detected
0 = No parity error detected
相關(guān)PDF資料
PDF描述
MC68HC908GR4MFA 8-BIT, FLASH, 8.2 MHz, MICROCONTROLLER, PQFP32
MC68HC908GR4VFA 8-BIT, FLASH, 8.2 MHz, MICROCONTROLLER, PQFP32
MC908GR8VFAR2 8-BIT, FLASH, 8.2 MHz, MICROCONTROLLER, PQFP32
MC68HC908GR4VP 8-BIT, FLASH, 8.2 MHz, MICROCONTROLLER, PDIP28
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MC68HC908GR4CP 制造商:Rochester Electronics LLC 功能描述:8 BIT MCU 4K FLASH - Bulk 制造商:Freescale Semiconductor 功能描述:8BIT 4K FLASH MCU 68HC908 DIP28
MC68HC908GR4CPE 制造商:Freescale Semiconductor 功能描述:
MC68HC908GR8ACFA 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Motorola Inc 功能描述: 制造商:MOTOROLA 功能描述:
MC68HC908GR8AMFA 制造商:Rochester Electronics LLC 功能描述:- Bulk
MC68HC908GR8AVFA 制造商:Rochester Electronics LLC 功能描述:- Bulk