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Revision History
MC68HC908GT16 MC68HC908GT8 Data Sheet, Rev. 3
4
Freescale Semiconductor
June,
2002
2.0
Figure 2-2. Control, Status, and Data Registers — Corrected ESCI arbiter data
register (SCIADAT) to reflect read-only status
Figure 14-19. ESCI Arbiter Control Register (SCIACTL) — Corrected address
location designator from $0018 to $000A
Figure 14-20. ESCI Arbiter Data Register (SCIADAT) — Corrected address
location designator from $0019 to $000B
Reformatted to meet current publications standards
1.5.6 ADC Reference Pins (V
REFH
and V
REFL
)
— Corrected connections
2.6.3 FLASH Page Erase Operation
— Updated procedure
2.6.4 FLASH Mass Erase Operation
— Updated procedure
2.6.5 FLASH Program/Read Operation
— Updated procedure
2.6.6 FLASH Block Protection
— Description updated for clarity
3.3.5 Conversion
— Updated for clarity
3.6.3 ADC Voltage Reference High Pin (V
REFH
)
— Corrected connections
3.6.4 ADC Voltage Reference Low Pin (V
REFL
)
— Corrected connections
3.7.1 ADC Status and Control Register
— Updated description of the COCO bit
Chapter 4 Configuration Register (CONFIG)
— Updated COP tmeout selections
Chapter 4 Configuration Register (CONFIG)
— Updted SSREC bit usage
Chapter 5 Computer Operating Properly (COP) Module
— Updated timeout
selections
Figure 5-1. COP Block Diagram
— Updated illustration for clarity
Table 6-1. Instruction Set Summary
— Updated definitions for STOP and WAIT
Figure 7-9. Code Example for Switching Clock Sources
— Replaced example
code
Figure 7-10. Code Example for Enabling the Clock Monitor
— Replaced example
code
Figure 14-18. ESCI Prescaler Register (SCPSC)
— Corrected address location
Chapter 15 System Integration Module (SIM)
— Clarified SIM features and
functionality
15.7.2 SIM Reset Status Register
— Clarified SRSR operation
Table 19-1. Monitor Mode Signal Requirements and Options
— Reworked
19.2.1 Functional Description
— Corrected Break description
19.3 Monitor Module (MON)
— Reworked
Chapter 20 Electrical Specifications
— Revised/added tables:
20.5 5.0-V DC Electrical Characteristics
20.6 3.0-V DC Electrical Characteristics
20.7 Supply Current Characteristics
20.8 5-V Control Timing
20.9 3-V Control Timing
20.20 Memory Characteristics
— Updated memory table
Chapter 20 Electrical Specifications
— Added figures:
Figure 20-1. RST and IRQ Timing
Figure 20-2. RST and IRQ Timing
50
170
171
September,
2004
3.0
Throughout
24
39
40
41
43
50
51
51
52
55
,
57
58
60
59
68
87
88
170
177
,
180
,
181
,
182
192
245
235
,
238
241
255
256
257
258
258
271
258
258
Revision History (Sheet 2 of 2)
Date
Revision
Level
Description
Page
Number(s)