參數(shù)資料
型號: MC68HC908JL8CSP
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDIP32
封裝: SDIP-32
文件頁數(shù): 35/56頁
文件大小: 648K
代理商: MC68HC908JL8CSP
MC68HC908JL8SM/D
MC68HC908JL8MC68HC908JK8
SCI Status
Register 2
BKF — Break Flag Bit
This clearable, read-only bit is set when the SCI detects a break character
on the RxD pin. In SCS1, the FE and SCRF bits are also set. In 9-bit
character transmissions, the R8 bit in SCC3 is cleared. BKF does not
generate a CPU interrupt request. Clear BKF by reading SCS2 with BKF set
and then reading the SCDR. Once cleared, BKF can become set again only
after logic 1s again appear on the RxD pin followed by another break
character. Reset clears the BKF bit.
1 = Break character detected
RPF — Reception in Progress Flag Bit
This read-only bit is set when the receiver detects a logic 0 during the RT1
time period of the start bit search. RPF does not generate an interrupt
request. RPF is reset after the receiver detects false start bits (usually from
noise or a baud rate mismatch) or when the receiver detects an idle
character. Polling RPF before disabling the SCI module or entering stop
mode can show whether a reception is in progress.
1 = Reception in progress
SCI Data Register
R7/T7–R0/T0 — Receive/Transmit Data Bits
Reading the SCDR accesses the read-only received data bits, R[7:0].
Writing to the SCDR writes the data to be transmitted, T[7:0]. Reset has no
effect on the SCDR.
NOTE:
Do not use read/modify/write instructions on the SCI data register.
SCI Baud Rate
Register
$0017
Bit 7
654321
Bit 0
BKF
RPF
Reset:
00000000
Figure 32. SCI Status Register 2 (SCS2)
$0018
Bit 7
654321
Bit 0
R7/T7
R6/T6
R5/T5
R4/T4
R3/T3
R2/T2
R1/T1
R0/T0
Reset:
Unaffected by reset
Figure 33. SCI Data Register (SCDR)
$0019
Bit 7
654321
Bit 0
SCP1
SCP0
R
SCR2
SCR1
SCR0
Reset:
00000000
Figure 34. SCI Baud Rate Register (SCBR)
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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