參數(shù)資料
型號: MC68HC912BL16FU8
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 16-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP64
封裝: QFP-64
文件頁數(shù): 19/128頁
文件大?。?/td> 3326K
代理商: MC68HC912BL16FU8
MC68HC912BL16TS/D
115
Figure 29 BDM Target to Host Serial Bit Timing (Logic 1)
Figure 29 shows the host receiving a logic one from the target MC68HC912BL16 MCU. Since the host
is asynchronous to the target MCU, there is a 0-to-1 cycle delay from the host-generated falling edge
on BKGD to the perceived start of the bit time in the target MCU. The host holds the BKGD pin low long
enough for the target to recognize it (at least two target E cycles). The host must release the low drive
before the target MCU drives a brief active-high speed-up pulse seven cycles after the perceived start
of the bit time. The host should sample the bit level about ten cycles after it started the bit time.
Figure 30 BDM Target to Host Serial Bit Timing (Logic 0)
Figure 30 shows the host receiving a logic zero from the target MC68HC912BL16 MCU. Since the host
is asynchronous to the target MCU, there is a 0-to-1 cycle delay from the host-generated falling edge
HC12A4 BDM TARGETTO HOSTTIM 1
HIGH-IMPEDANCE
EARLIEST
STARTOF
NEXT BIT
R-C RISE
10 CYCLES
HOST SAMPLES
BKGD PIN
PERCEIVED
START OF BIT
TIME
BKGD PIN
E CLOCK
(TARGET
MCU)
HOST
DRIVETO
BKGD PIN
TARGETMCU
SPEEDUP
PULSE
HC12A4 BDM TARGETTO HOST TIM 0
EARLIEST
STARTOF
NEXT BIT
E CLOCK
(TARGET MCU)
HOST
DRIVETO
BKGD PIN
PERCEIVED
START OFBIT TIME
10 CYCLES
HOST SAMPLES
BKGD PIN
TARGETMCU
DRIVE AND
SPEEDUP PULSE
HIGH-IMPEDANCE
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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