參數(shù)資料
型號： MC68HCL05C8A
廠商： Motorola, Inc.
英文描述： 8-Bit Microcontroller Units (MCU).(8位微控制器)
中文描述： 8位微控制器單元（MCU）。（8位微控制器）
文件頁數(shù)： 70/156頁
文件大?。?/td> 755K
代理商： MC68HCL05C8A
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Serial Communications Interface (SCI)
General Release Specification
MC68HC05C8A
—
Rev. 3.0
70
Serial Communications Interface (SCI)
MOTOROLA
9.5.2.4 Receiver Noise Immunity
The data recovery logic samples each bit 16 times to identify and verify
the start bit and to detect noise. Any conflict between noise-detection
samples sets the noise flag (NF) in the SCSR. The NF bit is set at the
same time that the RDRF bit is set.
9.5.2.5 Framing Errors
If the data recovery logic does not detect a logic one where the stop bit
should be in an incoming character, it sets the framing error (FE) bit in
the SCSR. The FE bit is set at the same time that the RDRF bit is set.
9.5.2.6 Receiver Interrupts
Three sources can generate SCI receiver interrupt requests:
1.
Receive Data Register Full (RDRF) — The RDRF bit in the SCSR
indicates that the receive shift register has transferred a character
to the SCDR.
2.
Receiver Overrun (OR) — The OR bit in the SCSR indicates that
the receive shift register shifted in a new character before the
previous character was read from the SCDR.
3.
Idle Input (IDLE) — The IDLE bit in the SCSR indicates that 10 or
11 consecutive logic 1s shifted in from the PD0/RDI pin.
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